J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. In International Workshop on Advanced Compiler Technology for High Performance & Embedded Systems, 2001.  Home/Search Document Details and Download
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Analysis of the Inuence of Register File Size on.. - Wehmeyer, Jain.. (2001) (Correct)
....[9] presents a framework enabling power analysis and investigation of the e ect of hardware modi cations as well as compiler optimizations. Their power analysis is based on parameterizable power models of common structures found in modern microprocessors. For VLIW architectures, Zalamea et al. [10] provide results concerning cycle time, area and power consumption for register les of di erent sizes. A number of approaches to ASIP design where the design space consists of a number of architectural parameters like number and kind of functional units, issue width and the size of caches have ....
J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. In Proc. of the International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems (IWACT), July 2001.
AND COMPILER MANAGEMENT OF ORGANIZATION AND COMPILER.. - Of The Requirements Self-citation (Zalamea Llosa Ayguade) (Correct)
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J. Zalamea, J. Llosa, E. Ayguade, and Mateo Valero. Software and hardware techniques to optimize register file utilization in VLIW architectures. In Proceedings of the International Workshop on Advanced Compiler Technology (IWACT'2001), July 2001.
Energy Aware Register File Implementation through - Instruction Predecode Jose (Correct)
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J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. In International Workshop on Advanced Compiler Technology for High Performance & Embedded Systems, 2001.
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE.. - Nagarajan, etal. (2004) (Correct)
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J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Software and hardware techniques to optimize register file utilization in VLIW architectures. In Proceedings of the International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems (IWACT), July 2001.
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE.. - Nagarajan, al. (2004) (Correct)
No context found.
J. Zalamea, J. Llosa, E. Ayguade, and M. Valero. Software and hardware techniques to optimize register file utilization in VLIW architectures. In Proceedings of the International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems (IWACT), July 2001.
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