| N. Nicolici, B. Al-Hashimi, A. Brown, "BIST Hardware Synthesis for RTL Datapaths Based on Test Compatibility Classes," IEEE Trans. on CAD, Vol. 19, pp. 1375-1385, Nov. 2000. |
....savings in power dissipation during test application in large scan sequential circuits is achieved with low computational time. Prior to investigating power minimisation techniques for testing low power VLSI circuits at RTL, Chapter 5 addresses testability of RTL data paths using BIST [139, 140, 144]. A new BIST methodology based on test compatibility classes achieves an improvement in terms of test application time, BIST area overhead, performance degradation, volume of test data, and fault escape probability over the traditional BIST embedding methodology described in Section 1.3.2. ....
....of low overhead in computational time. Finally, conclusions and directions for future research are given in Chapter 7. The previously outlined contributions in Chapters 3, 4, 5, and 6, and summarised in the final Chapter 7 have resulted in original work published or submitted for publication [139, 140, 141, 142, 143, 144, 145]. Motivation and Previous Work Personal mobile communications and portable computing systems are the fastest growing sectors of the consumer electronics market. The electronic devices at the heart of such products need to dissipate low power, in order to conserve battery life and meet packaging ....
N. Nicolici, B.M. Al-Hashimi, A.D. Brown, and A.C. Williams. BIST hardware synthesis for RTL data paths based on test compatibility classes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(11), November 2000.
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N. Nicolici, B. Al-Hashimi, A. Brown, "BIST Hardware Synthesis for RTL Datapaths Based on Test Compatibility Classes," IEEE Trans. on CAD, Vol. 19, pp. 1375-1385, Nov. 2000.
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