D. Boning and S. Nassif. Models of process variations in device and interconnect. In A. Chandrakasan, W. J.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....protocol himself, pretending to be the device. In our implementation of CPUFs, we use a silicon Integrated Circuit (IC) as the complex physical system from which we seek to extract PUF data. During IC fabrication, a number of process variations contribute to making each integrated circuit unique [6, 8]. These process variations have previously been used to identify ICs. For example, 17] uses random fluctuations in drain currents to assign an identifier to ICs. However, the identification system that results is not resistant to adversarial presence. An adversary can easily find out the ....

....studied silicon technology. This section describes the approaches that we have considered to make a PUF out of an integrated circuit (IC) Silicon PUFs try to harness the variations that are present when chips are fabricated. These variations and their sources are under constant research [6] as they determine the minimum feature size on ICs. In each new process, chip manufacturers do their utmost to reduce variation. Yet, with each generation, the relative variation increases (Chapter 14 of [8] This observation shows us that the process variation in ICs might be an excellent ....

D. S. Boning and S. Nassif. Models of Process Variations in Device and Interconnect. In W. Bowhill A. Chandrakasan and F. Fox, editors, Design of High Performance Microprocessor Circuits, chapter 6. IEEE Press, 2000.

....each IC, even if the digital IC functionality or masks of the ICs are exactly the same We rely on there being enough statistical delay variation for equivalent wires and devices across different ICs. Sources of statistical variation in manufacturing are well documented in the literature (e.g. [6] [5] and statistical variation has been exploited to create IC identification circuits that generate a single unique response for each manufactured IC [10] The transient response of the IC to a challenge, i.e. input stimulus, is de pendent on the delays of wires and devices within each IC. Our ....

....pressure variations, during the various manufacturing steps. The magnitude of delay variation due to this random component can be 5 or more. Delay variations of the same wire or device in different dies have been modeled using Gaussian distributions and other probabilistic distributions (e.g. [6]) Constant research attempts to reduce all these sources of variation because they inherently limit the component density of the IC. Nevertheless, the relative variations in state of the art components tends to increase with time (see chapter 14 of [7] On chip measurement of delays can be ....

D. S. Boning and S. Nassif. Models of Process Variations in Device and Interconnect. In A. Chandrakasan, W. Bowhill, and F. Fox, editors, Design of High Performance Microprocessor Circuits, chapter 6. IEEE Press, 2000.

....Engineering] Computer aided design. General Terms Algorithms 2 INTRODUCTION Over the years it has been widely acknowledged that the uncertainty about the true design and manufacturing conditions is a major cause of unnecessary over design and resulting underperformance of circuits [1][2] The sources of this uncertainty are manifold, and are due to the limitations of the actual design practices, uncertainty about the environmental design characteristics (cross talk noise, temperature and supply voltage variation) and the inherent variation of the underlying process ....

Boning, D., and Nassif, S., "Models of Process Variations in Device and Interconnect", in Design of High-Performance Microprocessor Circuits , A. Chandrakasan (ed.), 2000.

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D. Boning and S. Nassif. Models of process variations in device and interconnect. In A. Chandrakasan, W. J.

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