207 citations found. Retrieving documents...
C. E. Leiserson and J. B. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5--35, 1991.

 Home/Search   Document Not in Database   Summary   Related Articles   Check  

This paper is cited in the following contexts:

First 50 documents  Next 50

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED.. - With Efficient Initial   (Correct)

No context found.

C. E. Leiserson and J. B. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5--35, 1991.


High-Level Power Modeling, Estimation, and Optimization - Macii, Pedram, Somenzi (1997)   (22 citations)  (Correct)

No context found.

C. E. Leiserson, J. B. Saxe, "Retiming Synchronous Circuitry, " Algorithmica, Vol. 6, No. 1, pp. 5-35, 1991.


Minimum-Power Retiming for Dual-Supply CMOS Circuits - Farhana Sheikh Farhana (2002)   (Correct)

No context found.

C. Leiserson and J. Saxe. Retiming synchronous circuitry. Algorithmica, 6:5--35, 1991.


Enhanced Diameter Bounding via Structural Transformation - Baumgartner, Kuehlmann (2004)   (Correct)

No context found.

C. Leiserson and J. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, 1991.


Transformation-Based Verification Using Generalized Retiming - Kuehlmann, Baumgartner (2001)   (Correct)

No context found.

C. Leiserson and J. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5--35, 1991.


Physical Placement Driven by Sequential Timing Analysis - Aaron Hurst Philip (2004)   (1 citation)  (Correct)

No context found.

C. Leiserson and J. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5--35, 1991.


Min-Area Retiming on Flexible Circuit Structures - Baumgartner, Kuehlmann (2001)   (Correct)

No context found.

C. Leiserson and J. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5--35, 1991.


Temporal Decomposition for Logic Optimization - Nathan Kitchen Andreas (2005)   (Correct)

No context found.

C. Leiserson and J. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5--35, 1991.


N-Synchronous Kahn Networks - A Relaxed Model of.. - Cohen, Duranton..   (Correct)

No context found.

C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6(1), 1991.


The Esterel v5 Language Primer - Version v5_91 - Berry (2000)   (5 citations)  (Correct)

No context found.

C.E. Leiserson and J.B. Saxe. Retiming synchronous circuitry. Algorithmica, 6(1), 1991.


ACRES Architecture and Compilation - Ang, Schlansker (2004)   (Correct)

No context found.

C.E. Leiserson and J.B. Saxe. Retiming Synchronous Circuitry. Algorithmica, June 1991: pp. 5--35.


Loop Alignment for Memory Accesses Optimization - Fraboulet, Huard, Mignotte (1999)   (4 citations)  (Correct)

No context found.

C. E. Leiserson and J. B. Saxe. Retiming Synchronous Circuitry. In Algorithmica, volume 6, pages 5--35. SpringerVerlag, 1991.


Complexity of Multi-Dimensional Loop Alignment - Darte, Huard (2002)   (1 citation)  (Correct)

No context found.

C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6(1):5-35, 1991.


Loop Shifting for Loop Compaction - Alain Darte And (2000)   (1 citation)  (Correct)

No context found.

C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6(1):535, 1991.


Loop Shifting for Loop Compaction - Darte, Huard (1999)   (1 citation)  (Correct)

No context found.

C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6(1):535, 1991.


Layout Aware Retiming - Ranjan Srivastava Karnam (2001)   (1 citation)  (Correct)

No context found.

C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry", In Algorithmica, 1991, 6(1).


On Network Design Problems: Fixed Cost Flows and the.. - Even, Kortsarz, Slany (2001)   (Correct)

No context found.

C.E. Leiserson and J.B. Saxe. Retiming Synchronous Circuitry. Algorithmica, 6(1):5-35, 1991.


Approximating Minimum Feedback Sets and Multicuts in.. - Even, Naor, Schieber.. (1998)   (37 citations)  (Correct)

No context found.

C.E. Leiserson and J.B. Saxe, Retiming Synchronous Circuitry, Algorithmica, 6(1):5--35, 1991.


Compiler-Directed ILP Extraction for Clustered VLIW/EPIC.. - Pillai, al. (2003)   (Correct)

No context found.

C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. In Algorithmica, 1991.


Interconnect Planning with Local Area Constrained Retiming - Ruibing Lu And (2003)   (Correct)

No context found.

C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6:87--116, 1991.


Simultaneous Delay and Power Optimization for . . . - Ekpanyapong, Lim (2004)   (Correct)

No context found.

C. E. Leiserson and J. B. Saxe, "Retiming synchronous circuitry," Algorithmica, page 5-35, 1991.


An Industrial View of Electronic Design Automation - MacMillen, Butts.. (2000)   (Correct)

No context found.

C. E. Leiserson and J. B. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, no. 1, pp. 5--35, 1991.


Cycle-time Aware Architecture Synthesis of Custom Hardware.. - Sivaraman, Aditya (2002)   (5 citations)  (Correct)

No context found.

C. E. Leiserson and J. B. Saxe. Retiming Synchronous Circuitry. Algorithmica, 6(1):5-35, 1991.


The Esterel v5 Language Primer - Version v5_91 - Berry (2000)   (5 citations)  (Correct)

No context found.

C.E. Leiserson and J.B. Saxe. Retiming synchronous circuitry. Algorithmica, 6(1), 1991.


Combining Retiming and Recycling to Optimize the.. - Synchronous Circuits Luca   (Correct)

No context found.

C. E. Leiserson and J. B. Saxe. Retiming Synchronous Circuitry. Algorithmica, 6:5--35, 1991.

First 50 documents  Next 50

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC