E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In ICCAD-1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....design. The method has been automated and applied to a number of examples. 1 Introduction Asynchronous design styles are becoming increasingly popular because they offer the potential benefits of improved system performance, avoidance of clocking problems, low power operation, and modular design [8, 17, 18, 14, 26, 19, 21, 28, 2, 12, 15, 6, 27, 1]. However, the design of correct asynchronous circuitry is a difficult task since an asynchronous circuit can malfunction (i.e. produce unexpected behavior) during execution if it is not free of hazards, which correspond to undesired glitches in a circuit. This is in contrast with synchronous ....

E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In ICCAD-1989.

....of a comparable non hazard free method (espresso exacO. Overhead due to hazard elimination is shown to be negligible. 1 Introduction There has been renewed interest in asynchronous design because of the potential benefits of improved system performance, modular design, and avoidance of clock skew[22, 12, 18, 26, 13, 19, 7, 6, 2, 20, 25, 1]. However, a major obstacle to correct asynchronous design is the problem of hazards, or undesired glitches in a circuit. The elimination of all hazards from asynchronous designs is an important and difficult problem. Many existing design methods do not guarantee freedom from all hazards; other ....

E. Branvmd md R. F. Sproull. Translating concurrent programs into delay- insensitive circuits. In 1CCAD-1989.

....which extract more of the available silicon performance, and provide simple and efficient processing rateindependent interfaces. In an attempt to eliminate synchronous operating constraints, numerous asynchronous or self timed logic structures and design styles have been studied and implemented [1, 2, 4, 5, 6, 7, 8, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 26, 27, 28, 29, 30, 32]. Asynchronous or self timed systems promise a number of advantages over traditional synchronous systems: 1. adaptive operation, where the system s performance depends on actual (not worst case) voltage, temperature, process and data; 2. a wider environmental operating range, where the system ....

....of the appropriate dual rail signal (which is later reset) After all data inputs have been transformed into dual rail control signals, the cache protocol of Section 4.2 can be described by a burst mode specification. Note that many asynchronous specification styles have similar constraints, e.g. [4, 5, 6, 15, 17, 18, 19, 20, 30]. Each data input can be implemented in hardware as a dual rail pair of control inputs by simple gating of the input, and its complement, with a strobe signal. Such strobe signals are generated as outputs by the cache controller. This technique is similar to one used by Martin and Bums [5, 17, ....

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E. Brunvmd mid R. F. Sproull. Translating concurrent programs into delay- insensitive circuits. In 1CCAD-1989.

....the recognition of the possibility that the CAD tools can be used to to alleviate the designers from being overwhelmed by complex tasks, such as hazard free implementation and critical race free state assignment. As a result, a flurry of new asynchronous design styles and automatic synthesis tools [1, 4, 5, 6, 9, 12, 13, 14, 17, 21, 22] have been introduced to exploit these advantages in system design. There are roughly three distinct categories of asynchronoussynthesismethods available today: Transformations from HDL descriptions [1, 4, 12, 15] STG (Signal Transition Graph) SG (State Graph) synthesis [2, 5, 9, 13, 14, 21] ....

....new asynchronous design styles and automatic synthesis tools [1, 4, 5, 6, 9, 12, 13, 14, 17, 21, 22] have been introduced to exploit these advantages in system design. There are roughly three distinct categories of asynchronoussynthesismethods available today: Transformations from HDL descriptions [1, 4, 12, 15], STG (Signal Transition Graph) SG (State Graph) synthesis [2, 5, 9, 13, 14, 21] and multiple input change AFSM synthesis [6, 17, 23] Although asynchronous designs have been applied both to data path and control circuits, we believe that the highest payoff will come from applications to ....

E. Brunvand and R. F. Sproull. Translating concurrent programs into delayinsensitive circuits. In ICCAD-89.

....provided below. For a more complete discussion, the reader is referred to the literature [43] Delay insensitive (DI) circuits assume unbounded delays for both gates and wires; hence, they are very robust to component delay variations. The literature contains a large body of work on DI circuits [26, 77, 87, 35, 84, 13]. However, it has been shown that if one uses gate libraries with only single output gates, the class of DI circuits is severely restricted to those that use only the Muller C element, buffers and inverters [68] Practical DI circuits are, therefore, built using more complex multiple output ....

E. Brunvand and R. F. Sproull. Translating concurrent programs into delay- insensitive circuits. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pages 262-265, November 1989.

.... of asynchronous circuit target: locally clocked [23,11,6] delay insensitive [15,2,33,20] or various forms of sin91e and multiple input change circuits [31] Yet another distinction could be made on the nature of the control specification: graph based [24,18,34,4] programming language based [15,2,33,1], or finite state machine based [23,11] For the finite state machine based styles, there is a further distinction that can be made based on the method by which state variables are assigned [13,29] The design style space is large and each design style has its own set of merits and demerits. It ....

....the circuits. The approach taken in MEAT has therefore been to insure hazard free operation under sets of timing assumptions that can be verified as being within acceptable windows of fabrication and operational tolerance. Compiled implementations based on programming language like specifications [15,2,33,1], while elegant and robust, suffer in performance because they are presently compiled into intermediate library modules rather than into optimized transistor networks. The module of greatest concern is the C element. C elements are common circuit modules in asynchronous circuits and eliminating ....

Erik Brunvand and Robert Sproull. Translating Concurrent Programs into Delay-Insensitive Cir- cuits. In IEEE International Conference on Computer Aided Design: Digest of Technical Papers, pages 262 265. IEEE Computer Society Press, 1989.

....any explicit timing information. We want to support explicit timing information. Several researchers have used syntax directed translation to translate language based specifications into asynchronous circuits. Examples include Brunvand s work on translating Occam into macromodular micropipelines [7, 8], and also the Tangram[9] work at Philips. These techniques map program structures directly into a library circuit structures. Similarly, Kim, Lee and Lee[10] map program structures into a library of small signal transition graphs (STGs) These techniques 2 do not include an explicit HSE step ....

Erik Brunvand and Robert F. Sproull. Translating concurrent programs into delay-insensitive circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 262--265. IEEE Computer Society Press, November 1989.

....provided below. For a more complete discussion, the reader is referred to the literature [43] Delay insensitive (DI) circuits assume unbounded delays for both gates and wires; hence, they are very robust to component delay variations. The literature contains a large body of work on DI circuits [26, 77, 87, 35, 84, 13]. However, it has been shown that if one uses gate libraries with only single output gates, the class of DI circuits is severely restricted to those that use only the Muller C element, buffers and inverters [68] Practical DI circuits are, therefore, built using more complex multiple output ....

.... BURST MODE CIRCUITS 51 1 0 1 0 0 1 0 1 1 0 3 c s f f f x y q f p 1 4 5 10 7 x x p q y y [1,2] 1,2] 1,2] 6 9 8 000 111 xxx 111 000 xx0 111 xxx xx0 000 111 111 111 000 111 000 [2,3] 2,3] 2,4] 3,6] 1,2] 1,2] del[c] 3,5] del[c] [7,13] 2 Gate and wire delays shown are [min, max] Figure 3.4: 13 valued simulation and min max timing analysis. outputs (hX; X; 0i) although no global timing constraints have been violated. Therefore, these gates are marked (shown shaded in Fig. 3.4) Next, the second phase of operation of the ....

E. Brunvand and R. F. Sproull. Translating concurrent programs into delayinsensitive circuits. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pages 262--265, November 1989.

....that quickly estimate the area, performance, and energy dissipation of the final design by analyzing the Tangram program. Van Berkel s method also yields quasi delay insensitive circuits. Other translation methods from a CSP like language to a (quasi ) delay insensitive circuit can be found in [40, 41]. 12 4 A Typical Asynchronous Design In this section we present a typical asynchronous design, a micropipeline [42] The circuit uses single rail encoding with the two phase signaling protocol to communicate data between stages of the pipeline. The control circuit for the pipeline is a ....

E. Brunvand and R. F. Sproull, "Translating concurrent programs into delay-insensitive circuits," in Proc. International Conf. Computer-Aided Design (ICCAD), pp. 262--265, IEEE Computer Society Press, Nov. 1989.

....a comparable non hazard free method (espresso exact) Overhead due to hazard elimination is shown to be negligible. 1 Introduction There has been renewed interest in asynchronous design because of the potential benefits of improved system performance, modular design, and avoidance of clock skew [28, 15, 22, 38, 16, 23, 10, 8, 3, 24, 37, 2]. However, a major obstacle to correct asynchronous design is the problem of hazards, or undesired glitches in a circuit. The elimination of all hazards from asynchronous designs is an important and difficult problem. Many existing design methods do not guarantee freedom from all hazards; other ....

E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In IEEE International Conference on Computer-Aided Design, pages 262--265, November 1989.

....with redundant logic. Here we will focus on the alternative, which is to use explicit handshake signals for local synchronization. Because no absolute timing assumptions are made on the handshake, circuits are robust and easily composable, a property that has made this design approach popular [5, 9, 22, 26, 27, 30]. While the lack of global synchronization decreases the controllability of the circuit and thus makes an asynchronous circuit harder to test, the local synchronization tends to increase the observability. Consider the popular four phase handshake protocol, see Figure 3. A computation is started ....

....scan paths. The area increase is reported to be only approximately 6 . This approach seems appropriate if the cells are reasonable large. This is often the case for syntax directed synthesis methods where each cell corresponds to a language construct in a high level specification language (e.g. [5]) The feasibility of the scan approach for asynchronous circuits has been demonstrated in [33] with a 144 bit scan path in a systolic array. Asynchronous dual rail combinational logic, implemented as PLAs, can be made fully testable by introducing a dual rail scan path [12] However, 14] shows ....

Erik Brunvand and Robert F. Sproull. Translating concurrent programs into delay-insensitive circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 262--265. IEEE Computer Society Press, November 1989.

....[Nies88] into an intermediate form, which is referred to as a handshake circuit [VaBe92] A handshake circuit is a network of asynchronous components, the handshake processes, which communicate via channels. Handshake processes are directly mapped onto VLSI implementations. Brunvand and Sproull [Brun89] [Brun91] Brun91a] employ an occam like language to describe asynchronous systems. An occam like specification can then be compiled into an intermediate form using syntax directed translation, which after peephole optimization can be mapped onto a library of transition signalling components. 5.3 ....

Brunvand, E., Sproull, R. F., "Translating Concurrent Programs into Delay-Insensitive Circuits", Proceedings of ICCAD, 1989, pp. 262-265.

....[74] 13] 8] 75] 73] 76] An alternative approach has also been proposed, called timed circuits [77] which incorporates user specified timing information to optimize the circuits. Compiling asynchronous circuits from higher level programming languages has been extensively explored in [78], 79] 80] and these methods have been used to produce about two dozen functional ICs, including [81] 29] 37] 26, this issue] It would be an error to apply a regular synchronous technology mapper [82] to asynchronous circuits, because the mapper may introduce hazards in an otherwise ....

Erik Brunvand and Robert F. Sproull, "Translating concurrent programs into delay-insensitive circuits," in Proc. International Conf. Computer-Aided Design (ICCAD). Nov. 1989, pp. 262-- 265, IEEE Computer Society Press.

....for synthesis. Therefore, the specification method chosen can determine to a large extent the quality of the resulting circuit. Synthesis methods for languagebased specifications directly translate a program into a circuit. One approach to this, proposed by van Berkel in [68] and Brunvand in [15], is syntax directed translation where language constructs are mapped directly to library blocks. In this method, signal levels and concurrency are supported, but timing information cannot be specified. Also, the circuits produced tend to be redundant and slow since optimizations are not seen when ....

....Our technique does not find the region in its first iteration, however. It first finds a number of smaller regions before finding the final region that is a superset of all the rest. Therefore, although its performance is very good, it does not analyze the example instantaneously. Beta a [0,15] [0,15] a Alpha [0,15] Figure 9.6. TEL structures for the Alpha and Beta examples. One stage of the Beta example is composed of one state bit per stage with two events, one to set and one to reset the bit. In [13] Bozga shows that DBMs can only handle 4 stages while their technique can ....

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Brunvand, E., and Sproull, R. F. Translating concurrent programs into delay-insensitive circuits. In International Conference on Computer-Aided Design, ICCAD-1989 (1989), IEEE Computer Society Press.

....29 2 1 Introduction Process algebras have been successfully used for the specification and formal verification of digital asynchronous circuits. Several algebras based on the semantics of Hoare s CSP [Hoa89] and trace theory [vdS85] have been proposed for different delay models [Mar86, BS89, JU90, Ebe89, AG92] In CSP based algebras, the computation of a system is specified as a set of communicating processes that must be connected according to some discipline that guarantees a correct composition. Each language construct is hierarchically translated into a netlist of processes. ....

....a netlist of atoms that implement the unrefinable primitives of the language. Handshake components such as parallelizer and mixer used for the translation of TANGRAM [vB93] modules like decision wait , toggle and merge for delay insensitive algebras [JU90] or the macromodules in [BS89] and [GKBA94] are some illustrative examples of basic primitives. Skilled designers must provide an efficient implementation for each module according to the semantics of the language. The final circuit is then obtained by simply connecting the different modules by using the structural ....

E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In Proc. of the IEEE/ACM International Conference on Computer Aided Design, pages 262--265. IEEE Computer Society Press, November 1989.

....optimization, the BDD based synthesis gives results comparable in area to previous exact two level synthesis method. We also give a detailed example of the specified path optimization. 1 Introduction There have been many recent advances in asynchronous circuits and systems, both in tool design [1, 2, 4, 6, 9, 11, 13, 15, 16, 17, 18, 23, 24, 25] and actual systems design [3, 7, 8, 12, 13, 14, 19, 20] However, for maximum acceptability, it is imperative to be able to synthesize circuits that work with existing systems, which are largely made out of synchronous components. One particularly promising design style is the extended burst mode ....

E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In Proceedings of the 1989 IEEE International Conference on Computer Aided Design. IEEE Computer Society Press, 1989.

.... type of asynchronous circuit target: locally clocked[18, 10, 7] delay insensitive[13, 3, 23, 17] or various forms of single and multiple input change circuits[22] Yet another distinction could be made on the nature of the control specification: graph based[16, 4] programming language based[13, 23, 2], or finite state machine based[18, 10] For the finite state machine based styles, there is a further distinction that can be made based on the method by which state variables are assigned[11, 21] The design style space is large and each design style has its own set of merits and demerits. It is ....

....21] The design style space is large and each design style has its own set of merits and demerits. It is worthwhile to note that virtually all of the design styles focus on the design of the control path of the circuit. Compiled implementations based on programming language like specifications[13, 3, 23, 2], while elegant and robust, suffer in performance because they are presently compiled into intermediate library modules rather than into optimized transistor networks. A module of significant concern is the C element. C elements are common circuit modules in asynchronous circuits and eliminating ....

Erik Brunvand and Robert Sproull. Translating Concurrent Programs into Delay-Insensitive Circuits. In IEEE International Conference on Computer Aided Design: Digest of Technical Papers, pages 262--265. IEEE Computer Society Press, 1989.

....following properties: ffl Average case instead of worst case performance In a synchronous system, the maximal clock rate is determined by the slowest computation module. ffl Delay insensitivity The communication based on a selftimed handshake is reliable due to paradigm of delay insensitivity [2, 3, 4]. Hence, physical design variations may have no influence on the correctness of the circuit. Also, a better technology migration is possible. In synchronous systems, typical problems are clock skew and critical path estimation. ffl Modeling the environment Especially in the case of embedded ....

E. Brunvand and R. F. Sproull. Translating Concurrent Programs into Delay-Insensitive circuits. In Prof. of ICCAD, pages 262--265, 1989.

....low level signal transitions. Each annotated Petri net is then successively refined by syntactically allocating hardware resources (e.g. adders, incrementers, registers) for data related operations. This is similar to the macromodules approach used by existing high level asynchronous compilers [20, 13, 5, 1], except that we only use this approach for the data processing parts. In particular, we are using single rail encoded hardware modules that are organized with the data bundling assumption [17, 5, 1] These hardware modules can be controlled using either a four phase level signaling scheme or a ....

....is similar to the macromodules approach used by existing high level asynchronous compilers [20, 13, 5, 1] except that we only use this approach for the data processing parts. In particular, we are using single rail encoded hardware modules that are organized with the data bundling assumption [17, 5, 1]. These hardware modules can be controlled using either a four phase level signaling scheme or a two phase transition signaling scheme. We refer to the chosen control scheme as the primitive protocol . There is a growing consensus that the four phase scheme is more efficient, but our synthesis ....

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E. Brunvand and R. F. Sproull. Translating concurrent programs into delayinsensitive circuits. In International Conference on Computer-Aided Design, November 1989.

....allow each signal time to settle before other signals can change [41] This is called the fundamentalmode restriction. Burst mode extends fundamental mode to allow for a set, or burst, of inputs to arrive concurrently, followed by a burst of outputs [17, 35, 45] Another method, delay insensitive [12, 19, 33] assumes that the delays in wires and gates are unbounded. Speed independent circuits [6, 16, 32] are similar, but assume that wire delays are negligible. Most methods are based on the assumption that nothing is known about the delays between signal transitions. This means that the circuit must be ....

....these values is shown in Figure 2.7. The use of constraints is optional, but they are usually beneficial for large designs, because the more constrained a design is, the quicker a good solution can be found. A sample constraints specification is shown in Figure 2.8. drl myLib f ALU 32 452 [12,28,15] [12,30,16] Multiplier 32 671 [34,82,61] g Figure 2.6. Sample datapath resource library (DRL) constraints name f max area = val max delay = val resource name = val . resource name = val g Figure 2.7. Input format for constraints. 16 constraints myCon f max area = 923 max delay = ....

[Article contains additional citation context not shown here]

Brunvand, E., and Sproull, R. F. Translating concurrent programs into delay-insensitive circuits. In International Conference on Computer-Aided Design, ICCAD-1989 (1989), IEEE Computer Society Press.

....method chosen can determine to a large extent the quality of the resulting circuit. Synthesis methods for language based specifications directly translate a program into a circuit. One approach to this is syntax directed translation where language constructs are mapped directly to library blocks[1, 2]. In this method, signal levels and concurrency are supported, but timing information cannot be specified. Also, the circuits produced can be redundant and slow since optimizations are not seen when simply mapping program constructs to circuit blocks. In another language based method, the ....

.... j done ackline (ack k sendline#) req :ackline] ack#; process environment [req ; sendline] ackline ; sendline (done k ackline#) sendline] ackline [ sendline ack] req# k ackline# k done#) ack] j :sendline ackline# [sendline] ackline ; sendline sendline 1 [2,5] [2,5] done ackline ack [2,5] Circuit req ackline sendline 2 ack ackline req [2,5] done ackline [2,5] ackline [2,5] req ackline done [2,5] Conflicts: ack # sendline 1 sendline 2 # sendline 1 ack # sendline 1 req done ackline 3 ackline 1 ackline 1 ....

[Article contains additional citation context not shown here]

E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In International Conference on Computer-Aided Design, ICCAD-1989. IEEE Computer Society Press, 1989.

....two di erent groups require di erent design methods, and may generate di erent circuit implementations. The languages that are used to specify circuits include CSP [48] Occam [21] Tangram [13, 12] and VHDL [86] Language based approaches, such as those proposed by van Berkel [79] and Brunvand [22], often directly map language constructs to library blocks using syntax directed translation. The advantage of these approaches is the ability to describe large complex systems hierarchically and combat the state explosion problem by mapping language constructs directly into xed circuit modules. ....

Brunvand, E., and Sproull, R. F. Translating concurrent programs into delay-insensitive circuits. In International Conference on Computer-Aided Design, ICCAD-

....FPGAs. The two phase transition control modules and bundled data modules have been assembled from a library of macros designed to be used with the Actel parts [3, 2] The individual units of the NSR are designed to behave as pipeline stages that also process the information that flows through them [5, 4]. These parts were designed and implemented by students in a graduate seminar on VLSI architecture using the Workview suite of schematic capture and simulation tools from ViewLogic. The resulting FPGAs have been assembled as a wire wrapped prototype for testing and evaluation. The number of Actel ....

Erik Brunvand and Robert F. Sproull. Translating concurrent programs into delay-insensitive circuits. In ICCAD-89, pages 262--265. IEEE, November 1989.

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E. Brunvand and R. F. Sproull. Translating concurrent programs into delay-insensitive circuits. In ICCAD-1989.

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Brunvand E., Sproull R.F., Translating concurrent programs into delay-insensitive circuits. In ICCAD-89, pp.262-265, IEEE, November, 1989.

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