J. Spars, C. D. Nielsen, L. S. Nielsen, and J. Staunstrup. Design of Self-Timed Multipliers: A Comparison. In S. B. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 165--179. Elsevier Science Publishers, 1993. Home/Search Document Not in Database Summary Related Articles Check |
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A Standard-Cell Self-timed Multiplier for Energy and Area .. - Killpack, Mercer, Myers (2001) (Correct)
....This increases the latency of the multiply while substantially reducing the area. In [12] a delay insensitive design style is employed to remove internal glitches on all wires to save energy. However, it requires 2 wires to represent each bit in the multiplication, causing an increase in area. In [15], several self timed designs are compared, but all have considerable area penalty to achieve self timing. To remove the self timed area overhead, work in [8] employs a bundled data design style to implement an iterative multiplier. Bundled data design replaces the traditional xed frequency ....
J. Spars , C. D. Nielsen, L. S. Nielsen, and J. Staunstrup. Design of self-timed multipliers: A comparison. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 165-179. Elsevier Science Publishers, 1993.
A Low-Control-Overhead Asynchronous Differential Equation Solver - Kennethy Yun (1996) (1 citation) (Correct)
....adders. Because only the lower 16 bits of the 32 bit products are used, there is no need for a carry propagate adder to generate the upper 16 bits and no need for the lower half of the CSA array (as depicted in figure 3a) In many applications, multipliers are implemented in a pipelined fashion [7] in order to optimize the throughput. In this application, however, the latency must be optimized, not the throughput. We use a novel implementation technique called staggered evaluation (see figure 3b) to speed up the multiplication latency. In this scheme, the evaluation of each stage is delayed ....
J. Sparsø, C. D. Nielsen, L. S. Nielsen, and J. Staunstrup. Design of self-timed multipliers: A comparison. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 165--179. Elsevier Science Publishers, 1993.
Hardware Learning in Analogue VLSI Neural Networks - Lehmann (1994) (4 citations) (Correct)
.... problems associated with metastability (Seitz [213] Gabara et al. 73] In spite of the very attractive features of asynchronous systems, few conventional digital data processing systems have been successfully implemented because of the hardware overhead needed for handshaking (Spars et al. [227]) Pure analogue systems have no need for handshaking and are thus well suited to implement asynchronous systems. Though in systems with feed back the stability must be considered. Asynchronously operated analogue neural networks have been reported by Alspector et al. 9] Hollis and Paulos [98] ....
Jens Sparsø, Christian D. Nielsen, Lars S. Nielsen and Jørgen Staunstrup, "Design of Self-timed Multipliers: A Comparison," in Proc. IFIP TC10/WG10. 5 Working Conference on Asynchronous Design Methodologies, Manchester, pp. 165--179, 1993.
Asynchronous Design Methodologies: An Overview - Hauck (1995) (67 citations) (Correct)
....circuits include feedback in the form of state machines. Although the control structure for a micropipeline can be enhanced by using additional elements, this is a fairly complex and error prone activity. While several micropipelined solutions to specific circuit structures have been developed [17, 18, 19], including a complete asynchronous microprocessor [20] a general, higher level method for designing micropipeline control circuits is essential. 4. Delay Insensitive Circuits Delay insensitive circuits use a delay model completely opposite to the bounded delay model: they assume that delays in ....
J. Sparsø, C. D. Nielsen, L. S. Nielsen, J. Staunstrup, "Design of Self-timed Multipliers: A Comparison", Technical University of Denmark, Department of Computer Science Tech. Rep., 1992.
Asynchronous Techniques for Power-Adaptive Processing - Efthymiou (2002) (Correct)
No context found.
J. Spars, C. D. Nielsen, L. S. Nielsen, and J. Staunstrup. Design of Self-Timed Multipliers: A Comparison. In S. B. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 165--179. Elsevier Science Publishers, 1993.
Analysis and Characterization of a Locally-Clocked Module - Killpack (Correct)
No context found.
J. Spars, C. D. Nielsen, L. S. Nielsen, and J. Staunstrup, "Design of self-timed multipliers: A comparison," in Asynchronous Design Methodologies (S. Furber and M. Edwards, eds.), vol. A-28 of IFIP Transactions, pp. 165--179, Elsevier Science Publishers, 1993.
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