Steven M. Nowick, Davil L. Dill, "Exact Two--Level Minimization of Hazard--Free Logic with Multiple--Input Changes", ICCAD'92, pp. 626--630  Home/Search   Document Details and Download   Summary   Related Articles   Check

....one of the circuits in terms of area and energy. A more complete modeling of some of these circuits and parameters can be found in [29] The circuit examples in this paper contain static and domino gates normally employing a single pMOS device. Asynchronous tools such as ATACS [5] 3D [4] [30], and Petrify [2] can typically synthesize set reset flops and the appropriate functions [Fig. 1(a) We can often apply technology mapping into single variable reset (equivalently set) functions and implement them using standard footed domino gates as in Fig. 1(b) When the reset variable is not ....

....assumptions such as lazy transition systems [20] Global assumptions are dictated by the response of the environment. These assumptions can be applied manually, as in Section V C, or automatically, as in the burst mode assumption that a circuit will stabilize before a new input burst arrives [4] [30], 33] RT synthesis supports the creation and strengthening of timing assumptions by moving the relative positions of the heads and tails of arcs in a specification. If timing arcs are restricted to relative translations of behavioral arcs, aggressive timing optimizations can be performed on a ....

S. M. Nowick and D. L. Dill, "Exact two-level minimization of hazard-free logic with multiple-input changes," IEEE Trans. Computer -Aided Design, vol. 14, pp. 986--997, Aug. 1995.

....glitches. We also assume a pure delay (PD) model, which means we do not assume the presence of slow inertial delays to insure correctness. The two level minimization version of the problem has been addressed by a number of researchers in the past [25, 16, 10, 5, 3, 4, 11] More recently, Nowick [22] has developed an exact two level minimizer that combines a number of previous ideas on this problem. A limitation of the two level implementation approach is that it is not always possible to find a two level cover that can insure freedom from all static and dynamic hazards even though a ....

....with requirements for eliminating dynamic logic hazards for the dynamic transitions : 0 3 1 3 113 ) 1011. Specifically, the transition cube t5 = 11 0 1 intersects the transition cube of t4 = 0111; 1011] but it does not contain the start state 0111, which is a dynamic hazard violation. See [11, 4, 22] for more details. However, with the BDD approach, the above BDD implementation is also free of hazards for this transition (since it is a static transition) as well as the other specified transitions. 5.5 Synthesis from Free BDD s Although in the example shown in Section 5.4 we can find a ....

[Article contains additional citation context not shown here]

S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multipleinput changes. In ICCAD-1992.

....will not be invalidated when applied to the circuit under test. Combinational hazards have long received wide attention in the literature and have been attacked from a variety of directions, including hazard analysis [36] design of hazard free circuits via hazard elimination [4] 17] 23] and [24] among others, algebras for accurate hazard identification during vector simulation [10] and hazard free test generation [6] 18] 29] Combinational hazards are classified as either static or dynamic. Most of the original work focused on detecting and eliminating combinational hazards for ....

....3) This is also confirmed by our experimental results (Section 4) In this work we assume that gates and wires can have arbitrary finite delays, which means that the circuit operates correctly regardless of the delays of its gates or wires. This is known as the unbounded delay model [17] [24] since no bounded delay assumptions for correct operation or the use of delay elements to fix or filter out glitches are considered. A pure delay model is also assumed, where the presence of slow inertia is negligible and a pulse of any length can 4 propagate. This is a worst case model that ....

S. M. Nowick and D. L. Dill, "Exact two-level minimization of hazard-free logic with multiple-input changes", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 8, pp. 986-997, August 1995.

.... The target implementation is a pseudo static asymmetric CMOS complex gate per each output, known as generalized C element [3, 12] The synthesis algorithm generates hazard free covers for set and reset functions of each output using Nowick and Dill s exact hazard free logic minimization algorithm [14]. Each output circuit is formed by mapping its set and reset logic to N and P stacks of an asymmetric CMOS gate connected to a sustainer; long series stacks are decomposed into static gates followed by short stacks. A simple heuristic is used to ensure that no short circuit paths exist from V dd ....

....[19, 13] or multi level circuits reduced from multiplexor trees [20] These implementations are derived from on set covers of next state logic. These synthesis techniques produced efficient, high performance circuits for large specifications, utilizing a global logic minimization algorithm [14]. However, while attempting to synthesize circuits for specifications with very stringent performance requirements (as a part of the Asynchronous Instruction Decoder Project at Intel Corporation) it was determined that two level circuits may be inefficient in some cases. The natural course of ....

[Article contains additional citation context not shown here]

S. M.Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on Computer-Aided Design, 14(8):986--997, August 1995.

....be implemented as monotonic, hazard free circuits [2] However, when completion is determined by delay lines, monotonicity and hazards no longer matter. Thus, logic minimization can be applied, and the dual function is generated with an inverter, as in Fig. 12. Alternatively, hazard free logic [8,11] can be employed with a different control structure for the output registers. The single rail, four phase design style can also be readily synthesized (Fig. 13) The Load line is the delayed RDY line, rather than a function of many inputs. The VALID output is Load plus the register delay. Under ....

S.M. Nowick, D.L. Dill, "Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input Changes," ICCAD-92, Nov. 1992.

....to the AFSM synthesis capabilities of MEAT can be found in Section 4.7. The MEAT prototype did not remove all combinational hazards. A flaw was pointed out by Steve Nowick, who in the process proved that the burst mode methodology permits the synthesis of totally hazard free combinational logic [ND92] Nowick also went on to produce a burst mode synthesis system using local clocks [ND91a] as part of his Stanford dissertation. This interaction with Stanford also resulted in another burst mode synthesis system [YD92] A widely known method for formalizing and synthesizing AFSMs was developed ....

....as a direct result of the Post Office work. This includes research done at the HP science center at Stanford University. Several dissertations emanate from there [ND91b, YD92, SMD93] 5. Improved algorithms and methods for hazard free design have been developed as a result of this project [ND92] During the implementation phases of the Post Office project it became evident that automated synthesis tools are a necessary and viable alternative to hand layout for low latency asynchronous circuits. Once completed, MEAT produced circuit designs comparable in area and performance to the hand ....

[Article contains additional citation context not shown here]

Steven M. Nowick and David L. Dill. Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input Changes. In International Conference on Computer-Aided Design (ICCAD-92). IEEE Computer Society, 1992.

....but they must be avoided by a careful design of the logic and of its timing. Three main classes of asynchronous circuits avoid hazards purely by simple timing assumptions and by logical means, thus preserving as much as possible the above mentioned separation. 1) Fundamental mode circuits [1] [2], 3] assume that the environment of a circuit is so slow that the logic has time to stabilize before inputs can change again. Intuitively a fundamental mode circuit behaves similar to a synchronous one with a clock rate defined by the arrival of input patterns. Therefore the problem of avoiding ....

S. M. Nowick and D. L. Dill, "Exact two-level minimization of hazard-free logic with multiple-input changes," in Proc. Int. Conf. Computer-Aided Design, Nov. 1992, pp. 626--630.

....the sharing of a decomposed gate by different signal networks. The latter issues were successfully resolved in [8] but only within a standard architecture approach. Technology mapping for circuits working in fundamental mode [17] can be achieved by deriving a hazard free twolevel sum of products [14] and obtaining a multilevel form by hazard nonincreasing transformations [18] However, these transformations cannot be generally applied for the decomposition of speed independent circuits without introducing new hazards. In [15] technology mapping for speed independent circuits is done by ....

S. M. Nowick and D. L. Dill, "Exact two-level minimization of hazard-free logic with multiple-input changes," in Proc. Int. Conf. Computer-Aided Design, Nov. 1992, pp. 626--630.

.... feedback wires Figure 3: Example of a Huffman circuit of combinational logic implements the next state and output functions derived from a Flow Table specification, and feedback wires implement the state (see, e.g. Figure 3 and [5] 14] 2) Burst Mode Finite State Machine (FSM) circuits [12, 16]. 3) Bounded delay circuits synthesized from a Signal Transition Graph specification, where a block of combinational logic implements the next state function of each state and output function, and feedback wires implement the state (see, e.g. Figure 5 and [8] Huffman circuits. The synthesis ....

....( 3] to preserve both stuck at i and robust path delay fault testability. So the optimized circuit will also be testable (at least) for those two models using our strategy. Burst Mode Machines. Similar considerations apply to the synthesis algorithm for self clocked and 3 D circuits presented in [12] and [16] In this case, the specification is a Burst Mode FSM. Burst Mode FSMs restrict the class of allowed FSMs and of allowed environment behaviors with respect to [14] to prove the completeness of the algorithm. In a Burst ModeFSM, inputs and outputs are constrained to change in bursts, that ....

[Article contains additional citation context not shown here]

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In Proceedings of the International Conference on ComputerAided Design, November 1992.

....the sharing of a decomposed gate by di erent signal networks. The latter issues were successfully resolved in [8] but only within a standard architecture approach. Technology mapping for circuits working in fundamental mode [17] can be achieved by deriving a hazard free twolevel sum of products [14] and obtaining a multi level form by hazard preserving transformations [18] However, these transformations cannot be generally applied for the decomposition of speed independent circuits without introducing new hazards. In [15] technology mapping for speed independent circuits is done by merely ....

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In Proceedings of the International Conference on Computer-Aided Design, November 1992.

....under which a look up table based implementation of a macromodule is hazard free. Finally, we present the list of delay constraints that have to be satisfied by each asynchronous macromodule for a hazard free realization. 2 2. Background and Definitions The following definitions are taken from [13], which considers single output functions having binary input and output variables. Define B = 0,1 . A Boolean function, f, of n variables, x 1 , x 2 , x n , is defined as a mapping: f: B n B, for all 1 i n and x i e B. Each element in the domain B n of the function f is called a ....

....named combinational hazard[20] Combinational hazard can be classified into various classes: function, logic and essential hazards. 3.1. 1 Functional Hazards A function which does not change monotonically during a sequence of input changes is said to have a functional hazard for that input change[13]. Function hazards are a property of the logic function. They can only be eliminated through proper placement of delay elements, and arbitrary input and gate delays cannot be assumed. If a network has a function hazard for a given transition, then it cannot also have a logic hazard for the same ....

[Article contains additional citation context not shown here]

S.M. Nowick and D.L. Dill, "Exact Two-Level Minimization of Hazard-Free Logic with MultipleInput Changes," IEEE International Conference on Computer-Aided Design, p.626-30, 1992.

....and derive logic level equations or gate level networks that are hazard free under the assumption of some delay model. Burst mode asynchronous design techniques [16, 28, 27] automatically translate the high level descriptions into logic level equations, and by using transformation techniques [11, 17] or technology mappers [23] they create a technology specific gate level network. Speed independent design techniques from Signal Transition Graphs [6] and Change Diagrams (CDs) 25] assume the existence of an extensive library of complex gates without internal hazards to avoid the complexity of ....

Steven M. Nowick and David L. Dill. Exact two-level minimization of hazard-free logic with multipleinput changes. In Proc. of the IEEE International Conference on Computer Aided Design, pages 626--630. IEEE Computer Society Press, November 1992.

....Dill [ND91] guarantee hazard free implementations of asynchronous FSMs by using local clocking in the circuit. Yun et al. YDN92] present 3D state machines in which synthesis and hazard analysis is based on the construction of a three dimensional next state table. Nowick and Dill also present in [ND92] a QuineMcCluskey based method to generate two level hazard free logic. Kung presents in [Kun92] a set of optimization algorithms for multi level synthesis that maintain the hazard freeness of the original implementation. In the area of STGs, algorithms for hazard free synthesis have been ....

Steven M. Nowick and David L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In Proc. of the Int. Conf. on Computer-Aided Design, pages 626--630, 1992.

....hazards. Second, the state assignment must be free of critical races. Finally, the implementation must be free of combinational hazards. The exact hazard free logic minimization for two level combinational circuits, which solves the combinational hazard free problem, has been proposed by Nowick [ND92] A unicode single transition time state (USTT) state assignment which solves the critical race free assignment problem, was proposed by Tracey [Tra66] One important and difficult problem in designing hazard free asynchronous sequential circuits is to guarantee that the specification remains ....

....contains any essential hazard. One promising result obtained is that most of the building block elements in [Ung93, Sut89, Bru91] can be reduced to EHF flow tables. To synthesize a hazard free asynchronous circuits, a critical race free state assignment [Tra66] and hazard free logic minimization [ND92] must be applied to the EHF reduced flow table generated by EHF MinCover. ....

Steven M. Nowick and David L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In Proc. Int'l. Conf. Computer-Aided Design, pages 626--630. IEEE Computer Society Press, November 1992.

....improvement over the conventional method, which generates all hazard free primes. This paper is outlined as follows: In section 2 we introduce the basic principles of hazard free logic. Section 3 summarizes an exact method for generating hazard free prime implicants, proposed by Dill and Nowick [2]. Section 4 introduces a divide and conquer strategy which we will adapt to the ability to generate all hazard free prime implicants in section 5. Results and conclusions are given in section 6. 2 Background Hazard free logic is based on transitions. A transition consists of input variable ....

....clearly is implementation dependent, for example if the onset derived from the transition could be implemented by a single gate, there would be no hazard, hence the name logic hazard. In the case of 2 level logic hazards can be removed avoided by introducing so called required privileged cubes [2]. Required cubes ensure that during a transition for which an output is expected to remain constant at 1, there is a cube which enables the output during this transition. In the previous example, the required cube would be bd. Privileged cubes are required cubes, with an annotation. They are used ....

[Article contains additional citation context not shown here]

S.M.Nowick, D.L. Dill, Exact Two--LevelMinimization of Hazard--Free Logic with Multiple--Input Changes, ICCAD'92, pp. 626--630

....with synchronous ones, where possible. We also detail the methodology used to design the chip, and the asynchronous toolset that was created to support it. 1. Introduction Asynchronous logic design is currently receiving much attention as an alternative to traditional synchronous design [2] 5] [6], 7] 8] 9] 13] 14] Asynchronous designs do not use a global clock, simplifying global chip routing and eliminating problems due to clock skew. Furthermore, a large portion of a synchronous chip s power budget is dedicated to driving the clock, whereas elimination of the global clock in ....

....change in response to the last transition of a specified multiple input burst [4] Note that the set of transitions in an input burst can occur in any order, and at any time. This specification style has been shown to be practical for large designs and is the subject of active research ( 2] 5] [6], 7] 8] 9] A burst mode AFSM is specified by a state diagram consisting of a finite number of states, joined by directed arcs representing state transitions. Each arc is labeled with a set of input signal transitions, called an input burst, and a (possibly empty) accompanying set of output ....

[Article contains additional citation context not shown here]

S. M. Nowick and D. L. Dill. "Exact two-level minimization of hazard-free logic with multiple-input changes." In ICCAD, Proceedings of the International Conference on Computer-Aided Design, pages 626--630, 1992.

....into an input mapping cell (P i cell) and an output mapping cell (P z cell) The logic expressions of P i cell and P z cell are derived from the next state function and from outputs of the flow table, respectively. To implement the delay insensitive P module, hazard free logic minimization [9] is used to guarantee no glitch can be generated in any P module function. 10 01 X 0 i 1 i X 10000 00010 y 1 i 2 i 3 i 4 i 5 i y y y y y 1 i 2 i y 3 i y 4 i y 5 i y = X 0 i = 0 = 1 i X Pi cell y 1 i 2 i 3 i 4 i 5 i y y y y X 0 i 1 i X 1 2 3 1 0 0 0 1 0 0 0 1 10 01 X 0 i 1 i X 10 10 10 10 10 ....

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In Proc. International Conf. Computer-AidedDesign(ICCAD). IEEE Computer Society Press, Nov. 1992.

....we used back of the envelope techniques to decide amongst various mappings. This paper deals with the technology mapping of asynchronous burst mode control circuits. These circuits are specified with an extended burst mode (XBM) diagram and are implemented using a modified Huffman architecture [25, 26, 12]. As an example, the extended burst mode specification and implementation of the example scsi init send are given in Figure 1. This architecture has the advantage of very low latency because the input to output path is purely combinational, i.e. no explicit storage elements are rin fain ....

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multipleinput changes. IEEE Transactions on ComputerAided Design, 14(8):986--997, August 1995.

....hazards (transient errors due to stray delays) Most of the existing techniques rely on a high level specification of the system, and derive logic level or gate level networks that are hazard freeunder the assumption of some delay model. Burst mode design methodologies [8, 16] use transformations [6, 9] or technology mapping [13] to create a specific gate level network. Speed independent design methodologies from event models [3, 14] assume the existence of an extensive library of complex gates without internal hazards to avoid the technology mapping step. Varshavsky et al. 14] derived ....

Steven M. Nowick and David L. Dill. Exact two-level minimization of hazardfree logic with multiple-input changes. In Proc. ICCAD, pages 626--630, November1992.

.... The target implementation is a pseudo static asymmetric CMOS complex gate per each output, known as generalized C element [3, 12] The synthesis algorithm generates hazard free covers for set and reset functions of each output using Nowick and Dill s exact hazard free logic minimization algorithm [14]. Each output circuit is formed by mapping its set and reset logic to N and P stacks of an asymmetric CMOS gate connected to a sustainer; long series stacks are decomposed into static gates followed by short stacks. A simple heuristic is used to ensure that no short circuit paths exist from V dd ....

....[19, 13] or multi level circuits reduced from multiplexor trees [20] These implementations are derived from on set covers of next state logic. These synthesis techniques produced efficient, high performance circuits for large specifications, utilizing a global logic minimization algorithm [14]. However, while attempting to synthesize circuits for specifications with very stringent performance requirements (as a part of the Asynchronous Instruction Decoder Project at Intel Corporation) it was determined that two level circuits may be inefficient in some cases. The natural course of ....

[Article contains additional citation context not shown here]

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on Computer-Aided Design, 14(8):986--997, August 1995.

....the next state function c = ab c(a b) Its output, c, goes high (low) if both inputs, a and b, go high (low) otherwise, it keeps the previous value. 3. 3 Hazards A crucial problem which makes solution of logic decomposition problem for asynchronous design difficult is a problem of hazards [24, 22]. Recent development in [22] shows that if the so called Fundamental mode is acceptable (input cannot change until all internal circuit activity stabilizes) then most of the known methods of logic minimization can be gracefully extended to asynchronous hazard free minimization. These results can ....

....ab c(a b) Its output, c, goes high (low) if both inputs, a and b, go high (low) otherwise, it keeps the previous value. 3. 3 Hazards A crucial problem which makes solution of logic decomposition problem for asynchronous design difficult is a problem of hazards [24, 22] Recent development in [22] shows that if the so called Fundamental mode is acceptable (input cannot change until all internal circuit activity stabilizes) then most of the known methods of logic minimization can be gracefully extended to asynchronous hazard free minimization. These results can further be extended to FSMs ....

[Article contains additional citation context not shown here]

Steven M. Nowick and David L. Dill. Exact two-level minimization of hazard-free logic with multipleinput changes. IEEE Transactions on Computer-Aided Design, 14(8):986--997, August 1995.

....can be ignored. In all transitions, the outputs are generated directly in response to the inputs, and the local clock offers no hazard protection. Thus, the redundant cubes necessary in Huffman circuits are also needed for the output logic, and special care must be taken to avoid dynamic hazards [13]. The local clock generation logic may also contain similar hazards. Although this signal is not directly seen by the environment, a hazard on the clock lines could cause the state to change partially or completely when no change was intended. The locally clocked structure as presented so far ....

S. M. Nowick, D. L. Dill, "Exact Two-Level Minimization of Hazard-Free Logic with Multiple-Input Changes", in Proceedings of ICCAD, pp. 626-630, 1992.

....Hazards We can classify all hazards in combinational circuits into two categories: function hazards and logic hazards. Function hazards are due to an incorrectly specified function during multiple input changes. Logic hazards arise due to delay variations of the physical gates and wires [23, 17, 18, 20] despite the correct function. In 3D machines, we preclude the presence of function hazards by correctly specifying the next state of every reachable state [23] The requirements to insure hazard free combinational logic are presented in [23, 18] Initially, we assume that all input bursts are ....

....variations of the physical gates and wires [23, 17, 18, 20] despite the correct function. In 3D machines, we preclude the presence of function hazards by correctly specifying the next state of every reachable state [23] The requirements to insure hazard free combinational logic are presented in [23, 18]. Initially, we assume that all input bursts are unconditional. In 3D machines, the outputs change in response to the input bursts and remain constant while the fed back outputs and state variables change. Likewise, the state variables change due to the output bursts and remain constant while ....

[Article contains additional citation context not shown here]

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In ICCAD-92.

....and Verification of Multi Module Systems. Due to a clerical error, this research credit was omitted from the published version of this paper We apologize for this oversight. simple but efficient state encoding heuristic, and a procedure for generating constraints for exact logic minimization [11]. Finally, we demonstrate the effectiveness of the 3D implementation and the synthesis procedure using benchmark designs including a large realistic example (Asynchronous Data Transfer Protocol of the SCSI Bus Controller) 2 Overview 2.1 Specification An asynchronous state machine allowing ....

....(p, s) is an ordered pair of a privileged cube p and the start state s of the burst enabling a 1 0 transition of an output or a state variable, which p partially coYers. Logic minimization is performed using exact algorithms for hazard free logic, implemented in an automated logic minimizer [11]. This hazard free logic minimizer, using a variation of Quine McCluskey algorithm, attempts to find an optimum cover of essential cubes using logical prime implicants, the implicants that do not illegally intersect privileged cubes. Essential cubes, off set cubes and privileged pairs are ....

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In ICCAD- 92.

....of modern digital design. In asynchronous design, however, a key constraint is to provide hazard free logic, i.e. to guarantee the absence of glitches [38] Much progress has been made in developing hazard free synthesis methods, including tools for exact two level hazard free logic minimization [29], optimal state assignment [12] 31] synthesis for testability [28] and low power logic synthesis [24] However, these tools have been limited in handling large scale designs. In particular, hazard free two level logic minimization is a bottleneck in most asynchronous CAD packages. While the ....

....exact hazard free minimization, called IMPYMIN. Section VI presents experimental results and compares our approaches with related work, and Section VII gives conclusions. II. BACKGROUND The material of this section focuses on hazards and hazardfree logic minimization and is taken from [12] and [29]. For simplicity, we focus on single output functions. A generalization of these definitions to multioutput functions is straightforward and is described in [12] A. Circuit Model This paper considers combinational circuits, which can have arbitrary finite gate and wire delays (an unbounded wire ....

[Article contains additional citation context not shown here]

S. M. Nowick and D. L. Dill, "Exact two-level minimization of hazardfree logic with multiple-input changes," IEEE Trans. Computer-Aided Design, vol. 14, pp. 986--997, Aug. 1995.

....development of optimized CAD tools. In synchronous design, the development and implementation of CAD packages has been critical to the success of modern automated digital design. In asynchronousdesign, much progress has been made, including tools for: exact hazard free two level logic minimization [9], optimal state assignment [2] and synthesis for testability [8] However, these tools have been limited in handling large scale designs. In particular, while the exact hazard free minimization algorithm has been effective on small and medium sized examples, it has been unable to produce ....

....presents experimental results, and Section 6 gives conclusions. # This work was supported by NSF under Grant no. MIP 9308810 and by an Alfred P. Sloan Research Fellowship. 2BACKGROUND The material of this section focuses on hazards and hazard free logic minimization, and is taken from [2] and [9]. For simplicity, we focus on single output functions. A generalization of these definitions to multi output functions is straightforward, and is described in [2] Our heuristic minimizer handles multi output functions. 2.1 Circuit Model This paper considers combinational circuits having ....

[Article contains additional citation context not shown here]

S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-inputchanges. IEEE TCAD, CAD-14(8):986--997, August 1995.

....the synthesis of asynchronous state machines [9, 17, 8] These methods have been automated and produce low latency machines which are guaranteed hazard free at the gate level. The design tools have benefited from a number of hazard free optimization algorithms: exact two level logic minimization [10], multi level logic optimization [15, 3, 4] and technology mapping [13] However, none of these methods includes algorithms for optimal state assignment. The contribution of this paper is a general method for the optimal state assignment of asynchronous state machines. Optimal state assignment ....

....4 MULTIPLE VALUED FUNCTIONS AND HAZARDS For the following, we assume basic familiarity with the terminology of multi valued logic minimization (see [11] 4. 1 Circuit Model This paper considers combinational circuits having arbitrary finite gate and wire delays (unbounded wire delay model [10]) A pure delay model is assumed (see [15] 4.2 Multiple Valued Multiple Input Changes In this section, we generalize the notions of multiple input changes and transition cubes from the binary domain [10] to the multiplevalued domain. Definition 4.1 (Multiple valued transition cube) A ....

[Article contains additional citation context not shown here]

S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on CAD, 14(8):986--997, August 1995.

....of modern digital design. In asynchronous design, however, a key constraint is to provide hazard free logic, i.e. to guarantee the absence of glitches [38] Much progress has been made in developing hazard free synthesis methods, including tools for exact two level hazard free logic minimization [29], optimal state assignment [12] 31] synthesis for testability [28] and low power logic synthesis [24] However, these tools have been limited in handling large scale designs. In particular, hazard free 2 level logic minimization is a bottleneck in most asynchronous CAD packages. While the ....

....exact hazard free minimization, called Impymin. Section 6 presents experimental results and compares our approaches with related work, and Section 7 gives conclusions. II. Background The material of this section focuses on hazards and hazard free logic minimization, and is taken from [12] and [29]. For simplicity, we focus on single output functions. A generalization of these definitions to multi output functions is straightforward, and is described in [12] A. Circuit Model This paper considers combinational circuits having arbitrary finite gate and wire delays (an unbounded wire delay ....

[Article contains additional citation context not shown here]

Steven M. Nowick and David L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on CAD, CAD-14(8):986--997, August 1995.

....of hazard free two level logic. Such logic, in general, has two features which pose problems for testing: the presence of (a) nonprime implicants, and (b) redundancy. We first present background on combinational hazards and review an existing algorithm for hazard free two level logic minimization [11]. We then address the synthesis for testability problem by extending this algorithm in two ways. Our first algorithm finds a hazard free solution with exactly minimum number of non primes; our second algorithm finds a hazard free solution having exactly minimum redundancy. The two algorithms are ....

....discussion, a combinational circuit model is assumed where gates and wires may have arbitrary finite delays. Since we are concerned with the dynamic behavior of a combinational circuit as its inputs change value, we need to formalize the notion of a multiple input change . A transition cube [15, 12, 11] is a cube with a start point and an end point. Given input states A and B, the transition cube [A; B] has start (end) point A (B) and contains all minterms that can be reached during a transition from A to B. The cube describes a multiple input change or input transition from A to B. Inputs are ....

[Article contains additional citation context not shown here]

S. M. Nowick and D. L. Dill, "Exact two-level minimization of hazard-free logic with multipleinput changes," IEEE Trans. Computer-Aided Design, vol. 14, pp. 986-997, Aug. 1995.

....more than once. We examine the implications of allowing certain input changes to be non monotonic, define what a function hazard is in this setting, and explain how function hazards are avoided in the 3D implementations. B. 1 Definitions We summarize some definitions and concepts from [41] 42] [43], 44] that are used in the following subsections. A logic function f is a mapping from 0, 1 n to 0, 1, # . A minterm of f is an n tuple [x 1 , x 2 , xn ] where x i , the value of the i th input of f , is 0 or 1. The on set of f is the set of minterms for which f is 1; the ....

....next state IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 13 functions are completely and correctly specified, i.e. functionhazard free. In this section, we present two different methods to implement hazard free next state logic: the two level AND OR implementation [43] and the generalized C element implementation [34] d t = 0 t = d Pure delay model Inertial delay model Inverter Fig. 20. Delay models. The existence of hazards depends on the delay assumptions in the circuit model used and on the models of the delay itself. Many delay models have been ....

[Article contains additional citation context not shown here]

S. M. Nowick and D. L. Dill, "Exact two-level minimization of hazardfree logic with multiple-input changes," IEEE Transactions on ComputerAided Design, vol. 14, no. 8, pp. 986--997, Aug. 1995.

....in the transition (see [2] If a transition has a function hazard, no multiple valued implementation of the function is guaranteed to avoid a glitch during the transition, assuming arbitrary gate and wire delays. Therefore, we consider only transitions which are free of function hazards (cf. [14]) If f is free of function hazards for a transition from input A to B, an implementation may still have a logic hazard due to possible delays in the logic realization. Definition 2.2 (Required and privileged cubes) Given a multiple valued function f , and a set, T , of specified ....

S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on CAD, 14(8):986--997, August 1995. compats OPTIMISTA design i/s/o prime all DHF-PI's cons ms prods sec

....iff #(u, s) #(v, s) or #(u, s) # or #(v, s) #. u and v are dhf compatible (dynamic hazard free compatible) if no dynamic hazard results from specifying the next states of u and v on a single layer of the next state table. The notion of dhf compatibility was first introduced by Nowick in [10]. u and v are compatible (u # v) iff u and v are dhf compatible and, for every s in W X Y , 1. u, s) and (v, s) are output compatible and 2. #(u, s) # or #(v, s) # or #(u, s) # #(v, s) # is reflexive and symmetric but not transitive. Thus # is not an equivalence relation. ....

....two separate functions. Off set minterms of f set are off set minterms of f , and off set minterms of f reset are onset minterms of f . Logic minimization is performed using exact algorithms for hazard free logic, implemented in an automated logic minimizer originally developed by Nowick and Dill [10] and further enhanced by Fuhrer et al. [12] This hazard free logic minimizer, using a variation of Quine McCluskey algorithm [14] finds an optimal hazard free cover of required cubes using dynamichazard free implicants, implicants that do not illegally intersect privileged cubes. IV. ....

S. M. Nowick and D. L. Dill, "Exact two-level minimization of hazardfree logic with multiple-input changes," IEEE Transactions on ComputerAided Design, vol. 14, no. 8, pp. 986--997, Aug. 1995.

.... applied to some significant industrial examples: an adaptive routing chip [6] a cache controller [19] an infrared communications chip [1] and a SCSI controller [23] The design tools have benefited from a number of recent hazard free optimization algorithms: exact two level logic minimization [21], multi level logic optimization [29, 9, 11] technology mapping [27] and synthesis for testability [8, 22] However, none of these methods includes algorithms for optimal state assignment. The contribution of this paper is to present solutions to the optimal state assignment problem for ....

....C # B in column 01. Thus, although there are no transient points in the given state transition, the symbolic cover is constrained to include the product term 01 B,C , which is not part of the minimal solution. 2 2 This term is borrowed from algorithms for hazard free logic minimization [21], which set up a similar cube covering problem. 00 01 11 10 A A,0 A,0 D,0 A,0 111 B B,0 B,1 B,1 A,0 001 C A,0 B,1 C,1 C,0 100 D D,1 D,1 D,0 C,0 010 Figure 3. State table with critical race free assignment Symbolic Logic Minimization Algorithm Based on the above discussion, symbolic ....

[Article contains additional citation context not shown here]

S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, pages 626--630. IEEE Computer Society Press, November 1992.

....MIC machines, in any order and at any time. This relaxation considerably reduces the timing constraints placed on the environment, but nonetheless allows economical and high performance implementations. In particular, applying Nowick s method for exact two level hazard free logic minimization [25] yields low area, high performance circuits. Burst mode has been successfully used by both academia and commercial interests to design and implement a number of signicant circuits, for example, at Stanford, UCSD, HP, AMD and Intel. The specications are most easily illustrated by example. A ....

S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on CAD, 14(8):986997, August 1995.

....are valid; however, typically this is performed judiciously, so as to minimize logic area [9] improve performance, or reduce power consumption. By contrast, asynchronous machines must be encoded so as to avoid critical races [35] Further, if optimal logic is to be obtained, logic hazards [36][24] must be taken into account [11] Finally, to ensure correct operation, two level logic minimization for burst mode asynchronous machines must also take care to avoid logic hazards. Recent developments in this area include exact multi valued input (i.e. mvi) multi output minimization [11] fast ....

....synthesis systems, and compare them to Minimalist. The Uclock [23] system is a nearly complete path from plain burst mode specications to two level logic. It incorporates a safe, exact state minimization algorithm, and the rst exact hazard free singleoutput logic minimization algorithm [24]. Unlike Minimalist, however, it ooeers no automated method for 1 This is in fact a suOEcient, but not necessary, constraint. 5 Inputs: LIN, RIN, UIN; Outputs: LOUT, ROUT, UOUT; #Sn: 000 001 011 010 110 111 101 100 S0: S0,000 S3,010 , S1,010; S1: ....

[Article contains additional citation context not shown here]

S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In ICCAD, 1992.

....important aspect of these methods is the development of optimized CAD tools. In synchronous design, CAD packages have been critical to the advancement of modern digital design. In asynchronous design, much progress has been made, including tools for exact hazard free two level logic minimization [25], optimal state assignment [10, 27] and synthesis for testability [24] However, these tools have been limited in handling large scale designs. In particular, hazard free 2 level logic minimization is an important step in all the above mentioned CAD tools. However, while the currently used ....

....our approaches with related work, and Section 7 gives conclusions. Background information on BDD, ZBDDs, and implicit logic minimization can be found in the appendix. 2 Background The material of this section focuses on hazards and hazard free logic minimization, and is taken from [10] and [25, 23]. For simplicity, we focus on single output functions. A generalization of these definitions to multi output functions is straightforward, and is described in [10] 2.1 Circuit Model This paper considers combinational circuits having arbitrary finite gate and wire delays (an unbounded wire delay ....

[Article contains additional citation context not shown here]

Steven M. Nowick and David L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on CAD, CAD-14(8):986--997, August 1995.

....our approaches with related work, and Section 7 gives conclusions. Background information on BDD, ZBDDs, and implicit logic minimization can be found in the appendix. 2 Background The material of this section focuses on hazards and hazard free logic minimization, and is taken from [10] and [25, 23]. For simplicity, we focus on single output functions. A generalization of these definitions to multi output functions is straightforward, and is described in [10] 2.1 Circuit Model This paper considers combinational circuits having arbitrary finite gate and wire delays (an unbounded wire delay ....

....(i.e. set of implicants) of f whose AND OR implementation is hazard free for a given set, T , of specified input transitions. It is assumed below that the function is defined for all specified transitions; the function is undefined for all other input states. Theorem 2. 11 (Hazard Free Covering [23, 25]) A sum of products F is a hazardfree cover for function f for the set T of specified input transitions if and only if: a. No product of F intersects the OFF set of f ; b. Each required cube of f is contained in some product of F ; and (c. No product of F intersects any (non trivial) ....

[Article contains additional citation context not shown here]

S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, pages 626--630. IEEE Computer Society Press, November 1992.

....sending of another byte, while the second, to state 6 represents the signaling of the end of transmission. Using this design style, SCSI interfaces, cache controllers, an infrared communications controller, as well as a variety of interface specifications have been designed with promising results [9, 12, 17, 16, 18, 7]. This paper provides efficient algorithms for quantifying the energy consumption of burst mode circuits implemented with twolevel or multi level logic. Since different modes of circuit operation mayconsume different amounts of energy, we must determine the relative likelihood of executing ....

....storage elements such as latches, flip flops or C elements in a 3 D machine. 3. 3 Multi level implementations Multi level implementations of the combinational network implementing the next state functions can be derived from a BDD based synthesis [18] or from hazard free two level circuits [12] using hazard non increasing transformations [4] In both cases, the combinational circuits resulting from cutting feedback paths are guaranteed to be hazard free at the outputs under arbitrary wire delay assumption. Multi level logic may amplify the potential effect of hazards on energy ....

S.M. Nowick and D.L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on Computer-Aided Design, 14(8):986--997, August 1995.

....of this section is presented: a theorem that relates 3 valued simulatability of a circuit with hazard freedom of asynchronous circuits. In particular, it is shown that our new constraints on logic synthesis for initializability correspond precisely to hazard free synthesis requirements (cf. Nowick [16], Eichelberger [15] Finally, a multi level synthesis method for initializability is presented that leverages off of existing hazard free synthesis methods. 6.1 How logic synthesis affects 3 valued simulatability The following example illustrates how logic synthesis can affect logical ....

....on the one hand, and hazard freedom on the other. Example 6.1 showed that it is sometimes necessary to include a certain product term in the 2 level implementation for initializability. In that example, bc was such a product term in the implementation for Y . In the asynchronous terminology of [16], bc is called a required cube; the stipulation that the 2 level implementation of Y must include at least one term that covers bc is a hazard free covering requirement. We now point out the correspondence between 3 valued simulatability and hazard freedom for the synthesized circuit of Fig. 8. ....

[Article contains additional citation context not shown here]

S.M. Nowick and D.L. Dill, "Exact Two-level Minimization of Hazard-free Logic with Multiple-Input Changes," IEEE Trans. CAD, vol. CAD-14, pp. 986--997, Aug. 1995.

....the implications of allowing certain input changes to be nonmonotonic, define what a function hazard is in this setting, and explain how function hazards are avoided in the 3D implementations. CHAPTER 3. HAZARD CONSIDERATIONS 39 3.3. 1 Definitions We summarize some definitions and concepts from [5, 4, 53, 60] that are used in the following subsections. A logic function f is a mapping from f0; 1g n to f0; 1; g. A minterm of f is an n tuple [x 1 ; x 2 ; x n ] where x i , the value of the i th input of f , is 0 or 1. The on set of f is the set of minterms for which f is 1; the off set of f is ....

....be introduced by the delay variations of physical gates and wires, even if the logic functions are completely and correctly specified, i.e. function hazard free. In this section, we present two different methods to implement hazard free combinational logic: the two level AND OR implementation [53] and the multiplexor tree implementation derived from a Binary Decision Diagram (BDD) representation of the next state function [35] d Inverter t = 0 t = d d Inertial delay model Pure delay model Figure 3.6: Delay model. The existence of hazards depends on the delay assumptions in the circuit ....

[Article contains additional citation context not shown here]

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In Proceedings of the 1992 IEEE/ACM International Conference on Computer Aided Design, pages 626--630, November 1992.

....we develop a set of hazard free covering requirements for the 2 level AND OR implementation of a logic function during a multiple input change with some inputs undergoing non monotonic transitions. The hazard free combinational logic synthesis for multiple monotonic input changes is described in [13, 21]. The new results presented here are simple extensions of [13] We apply these results to the 3D machine combinational logic synthesis. Delay Model The bounded wire delay model best represents the Huffman mode asynchronous state machines, such as the 3D machines, in the current generation of ....

....AND OR implementation of a logic function during a multiple input change with some inputs undergoing non monotonic transitions. The hazard free combinational logic synthesis for multiple monotonic input changes is described in [13, 21] The new results presented here are simple extensions of [13]. We apply these results to the 3D machine combinational logic synthesis. Delay Model The bounded wire delay model best represents the Huffman mode asynchronous state machines, such as the 3D machines, in the current generation of VLSI technology (ever decreasing feature size and non trivial ....

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In ICCAD-92.

No context found.

Steven M. Nowick, Davil L. Dill, "Exact Two--Level Minimization of Hazard--Free Logic with Multiple--Input Changes", ICCAD'92, pp. 626--630

No context found.

S. M. Nowick and D. L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on Computer-Aided Design, 14(8):986--997, Aug. 1995.

No context found.

S. Nowick and D. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In ICCAD- 1992.

No context found.

S.M. Nowick and D. L. Dill, "Exact two-level minimization of hazard-free logic with multiple-input changes," in International Corference on Computer-Aided Design, IEEE, [992.

No context found.

S.M. Nowick and D. L. Dill, "Exact two-level minimization of hazard-free logic with multiple-input changes," in International Corference on Computer-Aided Design, IEEE, [992.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC