P. Michel, U. Lauther, P. Duzy, "The Synthesis Approach To Digital System Design," Kluwer Academic Publishers, 1992  Home/Search   Document Not in Database   Summary   Related Articles   Check

....System Design Laboratory v Publications not included in the thesis Related papers [1] M. O Nils, J. berg, A. Jantsch, Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces , poster paper) In Proc. of EuroMicro 98, Vol. I, pp. 55 58, Vsters, Sweden, Aug. 25 27, 1998. [2] J. berg, A. Jantsch, A. Hemani, Validation of Interface Protocols Using Grammar based Models , In the Proc. of the IEEE International High Level Design Validation and Test Workshop (HLDVT 98) pp. 40 46, La Jolla, California, Nov. 12 14, 1998. 3] J. berg, P. Ellervee, A. Hemani, Grammar based ....

....automation begins around the time when the first computers come, but it was not until the end of the 70s that the computer systems were becoming advanced enough to handle bigger design problems. Before 1979, about 40 the effort in designing a 20 kGates circuit was spent in the physical design [2]. Around the year 1983, tools for performing placement and routing had appeared on the market, reducing the time spent for physical design from 70 Person Months to 2. At the same time had improvements on the system design reduced from 40 to 30 Person months by the introduction of simulation and ....

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P. Michel, U. Lauther, P. Duzy, editors, "The Synthesis Approach to Digital System Design", Kluwer Academic Publishers, 1992, ISBN 0-7923-9199-3.

....x ) z, x) where ( indicates two concurrent assignment operations. 3. PROCESS DESIGN In this section we will describe the processes of evaluation and selection of the moves at a lower abstraction level. We will adopt a symbolic language derived from a silicon Figure 2 Figure 3 compiler [12] and, as we said before, we will consider to have an external unit to evaluate the o.f, called Objective Function Computation Unit, OFCU. Each move value depends on the variation a move inducts in the o.f. value and on its tabu status (see figure 4) This unit computes the move value as well as ....

P. Michel, U. Laughter, P. Duzy, "The synthesis approach to digital system design", Kluwer Academic Publishers, second printing, 1995.

....(components) of existing older designs. Related to the reuse is the cost of maintenance, i.e. it is essential that the specification is easy to read and is well documented. 2 Before 1979, about 40 of design efforts was spent in the physical design phase when designing a 20 kgate circuit [MLD92] In four years, placement and routing tools arrived onto the market and thus effectively reducing the physical design phase from 70 to 2 person months. The other improvements plus simulators reduced the system and logic design phases by 20 in total. The introduction of hierarchy and hardware ....

....to be synthesized, or a part of it, is specified in terms of its behavior as an algorithm. Due to this, HLS is also called as behavioral synthesis. The relation between HLS and the other synthesis phases is best described by Figure 1.1. Efforts needed to design a 20 kgate circuit (Modified from [MLD92] System 1979 1983 1986 1988 92 1992 95 40 60 70 30 50 2 Design Logic Design Physical Design Schematic Entry Hierarchy, Generators 30 40 2 30 2 10 2 High Level System Level Synthesis Simulation Placement Routing Logic Level Synthesis 3 2 Specialized High Level Synthesis 1996 . 3 ....

P. Michel, U. Lauther, P. Duzy, editors, "The Synthesis Approach to Digital System Design", Kluwer Academic Publisher, 1992, ISBN 0-7923-9199-3.

....set of resources at which time the next instruction can be issued. Since even quite simple scheduling problems are NP complete, many heuristics exist to resolve such problems. Generally they are based on DFG s or CFG s. Techniques as As Soon As Possible (ASAP) or as As Late As Possible (ALAP) [MLD92] order the operations according to their data dependencies represented by a DFG. If there are different mappings for an operation, the task is executed as soon as possible or as late as possible. In addition List Scheduling [MLD92] uses the topological order given by a priority criterion or by the ....

....as As Soon As Possible (ASAP) or as As Late As Possible (ALAP) MLD92] order the operations according to their data dependencies represented by a DFG. If there are different mappings for an operation, the task is executed as soon as possible or as late as possible. In addition List Scheduling [MLD92] uses the topological order given by a priority criterion or by the mobility of a task. The mobility of an operation is the difference between the earliest and the latest possible schedule. Jobs possessing a higher priority or a lower mobility are preferred. The pipeline synthesis tool SEHWA ....

P. Michel, U. Lauther, P. Duzy, "The synthesis approach to digital system design", Kluwer Academic Publishers, 1992

....support the designer in applying them, 9 the fabrication of more and more complex electronic systems has been made possible in recent years. Those tools allow designers to move higher and higher levels of abstraction. In order to manage complexity, the design process can be decomposed according to [MLD92] into a series of subtasks, which deal with different issues. 1. System level synthesis: The specification of the system at the highest level of abstraction is given by its functionality and a set of implementation constraints. The task of this step is to decompose the system into several ....

P.Michel, U.Lauther, P.Duzy, "The Synthesis Approach To Digital System Design," Kluwer Academic Publishers, 1992

....with the path initialization in step 9. So in this algorithm the Q0 parameter which can be found in normal state transition rule was eliminated. 4. Problem We select Differential Equation Solver as our problem for testing this algorithm. It was used as an example in various literatures [1] [2], 5] 18] Input to the algorithm was a CDFG that will numerically solve the equation y 3xy 3y = 0. In this experiment, we use the target architecture as in [2] which are combinational functional units (except the pipeline functional unit) distributed registers, multiplexers or ....

....Differential Equation Solver as our problem for testing this algorithm. It was used as an example in various literatures [1] 2] 5] 18] Input to the algorithm was a CDFG that will numerically solve the equation y 3xy 3y = 0. In this experiment, we use the target architecture as in [2], which are combinational functional units (except the pipeline functional unit) distributed registers, multiplexers or unidirectional buses. All registers use the same clock edge. We also put the constraint that each register and functional unit has only one bus per input as in [10] A wire, ....

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Michel, Petra., Lauther, Ulrich. and Duzy, Peter. The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, 1992.

.... exploration and trade off analysis between different design alternatives can only be achieved if fast and accurate area and delay estimators exist for evaluating selected components; such estimators are crucial to the success and acceptance of highlevel synthesis as a design methodology [GDWL92] [MiLD92]. High Level Synthesis typically relies on a library of well defined, parameterized RT component generators to simplify the mapping of behavioral variables and operators to physical components. These parameterized components are used as the building blocks for the tasks of allocation and binding. ....

P. Michel, U. Lauther and P. Duzy (Editors) "The Synthesis Approach to Digital System Design," Kluwer Academic Publishers 1992.

....4.2. Legend ALU2 Mult.2 clock cycles Mult.1 ALU1 ax dx y u r1 r2 r3 Registers Input r1 r2 BEHAVIORAL SYNTHESIS FOR LOW POWER 49 All the three main problems of behavioral synthesis, resource allocation, resource assignment and operation scheduling, are NP complete in the general case [Mic92]. These three tasks can be performed, in principle, in any order. They also can be solved together, which makes the problem harder, but offers a potentially wider choice of efficient solutions. Often, there are constraints imposed on parameters influencing the solution choice. Such parameters are, ....

....a solution to the system level synthesis problem, as we defined it above, implies processor bus allocation, task communication scheduling, and assigning tasks communications to processors buses in one synthesis step. Each of these problems, taken separately, is NP complete in the general case [Mic92]. Although the heuristic methods we used can not guarantee optimal solutions, they perform quite well as the experiments presented later on are showing. 5.3.2 RESULTS In order to evaluate the design alternatives from the energy consumption point of view, we used an example introduced in [Pra92] ....

Michel, P.; Lauther, U.; Duzy, P., The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, 1992.

....x) where ( indicates two concurrent assignment operations. 3. PROCESS DESIGN In this section we will describe the processes of evaluation and selection of the moves at a lower abstraction level. We will adopt a symbolic language derived from a silicon Figure 2 Figure 3 Figure 4 compiler [12] and, as we said before, we will consider to have an external unit to evaluate the o.f, called Objective Function Computation Unit, OFCU. Each move value depends on the variation a move inducts in the o.f. value and on its tabu status (see figure 4) This unit computes the move value as well as ....

P. Michel, U. Laughter, P. Duzy, "The synthesis approach to digital system design", Kluwer Academic Publishers, second printing, 1995.

....is assumed to be able to only perform one function at a time, i.e. generates a single output and is associated to a single behavioral operator for a time step. Most behavioral synthesis tools are based on this assumption, e.g. MIMOLA [Marw86] ADAM [GrKP85] and the systems described in [CaWo91] [MiLD92]. At the logic synthesis level, Takagi [Taka85] describes a representation of complex RT components using templates, and uses these templates to synthesize gate level structures. BeCM92] describe a similar template representation scheme using VHDL macros for sequential logic synthesis. However, ....

P. Michel, U. Lauther and P. Duzy, The Synthesis Approach to Digital System Design, Kluwer, 1992.

....process. New techniques covering test and synthesis (Test Synthesis) 1] are appearing but their application is mainly oriented to gate level (commercial tools such as Synopsys) On the other hand, most high level synthesis tools do not take into account the testability of the final architecture [3]. This paper presents a high level synthesis system which includes testability improvement among its goals. The aforementioned system generates loop free circuits and are, therefore, easily testable with partial scan techniques. In order to achieve this, a complete RT level loop classification is ....

....are the scheduled data flow graph (SDFG) and the compatibility graphs of variables and operations. The output of the algorithm is the RT structure and a list of the registers to be scanned. Said algorithm, called LOOPALLOC, is a modification of the weight directed clique partitioning algorithm [3] where the weight w of an edge of the compatibility graph is 1 when that assignment does not form any loop and 0 when it forms it. In order to know if an assignment creates a loop, the algorithm manages an oriented graph internal representation (figure 6) With this representation all the loops in ....

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P. Michel et al:"The Synthesis Approach to Digital System Design". Kluwer Academic Publishers. 1992.

....tool [Camposano 91] Some design requirements can, however, impose particular restrictions on the execution time of an operation or a sequence of operations in the algorithmic description, on the execution frequency of a signal input output, on the timing properties of interface signals, etc. Michel 92] Requirements on the timing aspects of the design are incorporated as timing constraints in the behavioral specification submitted to the synthesis system. These constraints have to be captured as part of the internal design representation generated after compilation of the input specification. ....

P. Michel, U. Lauther, P Duzy, The Synthesis Approach to Digital System Design, Kluwer Academic Publisher, 1992.

....been partially supported by the Swedish National Board for Industrial and Technical Development (NUTEK) 1994 94 36 1 1. Introduction Complex hardware circuits often require some timing restrictions to be incorporated in their behavioral specification for high level synthesis [Gajski 92, Michel 92] These constraints have to be captured as part of the internal design representation generated after compilation of the input specification and timing analysis has to decide if the constraints are consistent and if operation scheduling according to the imposed restrictions can be performed ....

P. Michel, U. Lauther, P Duzy, The Synthesis Approach to Digital System Design, Kluwer Academic Publisher, 1992.

....exploration phase. Future research will concentrate on automating this design decision. Comparison with other approaches The synthesis process used within the MOVE framework has much in common with high level synthesis (HLS) systems which have been developed [Bre91, Cam90, CW91, GDWL92, KGD90, MLD92, WC91] they both aim at the automatic mapping of a functional specification into a structural description. There are several differences, though: ffl Most HLS systems do not accept full blown applications written in commonly used imperative languages. Usually their usage is restricted to ....

Petra Michel, Ulrich Lauther, and Peter Duzy, editors. The synthesis approach to digital system design. Kluwer Academic Publishers, 1992.

....registers. Compatibility graphs can be used to represent life cycles that do not overlap; clique partitioning of the compatibility graph yields a set of registers. Both coloring and clique partitioning are NP complete. However, efficient heuristics have been discovered for solving both problems. [3, 4, 5, 6] Register optimization techniques can be broadly classified into two categories: value based and carrier based. In the value based approach, register optimization is modeled as the problem of mapping data values produced and used by operations in a data flow graph representation of the ....

Petra Michel, Ulrich Lauther and Peter Duzy, "The Synthesis Approach to Digital System Design", Kluwer Academic Publishers, 1992.

....features may be packed into a cost function to be reduced by the allocation algorithm. This is similar to the binding allocation of functional units in classic high level synthesis tools [11] 18] 3 Most of the allocation algorithms used in high level synthesis may be used to solve this problem [24]. c h1 RPC c f1 c3 c2 c1 P1 P2 P3 P4 Communication network protocol RPCall svc3 c f1 RPCall svc1 c h1 RPCall svc1 c h1 RPCall svc1 c h1 RPCall svc3 c f1 RPCall svc2 c h1 RPCall svc2 c h1 RPCall svc4 c s1 Fig. 5. System after allocation of communication units c h4 RPC c f2 c1 ....

P. Michel, U. Lauther, and P. Duzy, The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, 1992.

....synthesized TTAs require far less connectivity and fewer register ports than more traditional instruction level parallel architectures. Related work The synthesis process used within the MOVE framework has much in common with high level synthesis (HLS) systems which have been developed (see e.g. [3, 9, 27, 34]) they both aim at the automatic mapping of a functional specification into a structural description. There are several differences, though: 1. Most HLS systems do not accept full blown applications written in commonly used imperative languages. Usually their usage is restricted to input from ....

Petra Michel, Ulrich Lauther, and Peter Duzy, editors. The synthesis approach to digital system design. Kluwer Academic Publishers, 1992.

....all purpose high level synthesis systems available today. Among them are the Synopsis Behavioral Compiler [Kna 95] and SYNT from Synthesia (based on the techniques described in [Hem 92] An excellent introduction to the area of highlevel synthesis of digital systems is given in both [Gaj 92] and [Mic 92] Program gcd; begin read(x, y) if (x 0) and (y 0) then repeat while (x = y) x : x y; swap(x, y) until(y = 0) end; Figure 2.1: Transformation from the algorithmic to the circuit level. High level synthesis Register transfer Logic level synthesis R1 R2 ALU Layout 13 2.2 The ....

....done by applying the system to a set of well established benchmarks. In this chapter the unicycle and multicycle scheduling in combination with the module allocation and binding are applied to the fifth order digital elliptic wave filter [Pen 94] and the 256 point Discrete Fourier Transform (DFT) Mic 92] benchmarks. The results are compared with those given by the ARIEL [Abr 91] SALSA [Nes 93b] and original CAMAD [Ele 95] high level synthesis systems. The used module library is based on the LSI 10K technology and the experiments have been carried out on a SPARCstation 10. 7.1 The Elliptical ....

P. Michel, U. Lauther, P. Duzy, " The Synthesis Approach to Digital Systems Design," Kluwer Academic Publishers, 1992.

.... space exploration and trade off analysis between different design alternatives can only be achieved if fast and accurate area and delay estimators exist for evaluating selected components; such estimators are crucial to the success and acceptance of high level synthesis as a design methodology [9] [19]. High Level Synthesis typically relies on a library of well defined, parameterized RT component generators to simplify the mapping of behavioral variables and operators to physical components. These parameterized components are used as the building blocks for the tasks of allocation and binding. ....

P. Michel, U. Lauther and P. Duzy (Editors) "The Synthesis Approach to Digital System Design, " Kluwer Academic Publishers 1992.

....(HLS) as a translation process from a behavioral description into a register transfer level (RTL) structural description. High level synthesis has been a very hot research topic over the past fifteen years. Comprehensive discussions of specific re2 search approaches to HLS can be found in [6, 20, 63, 96]. We concentrate on its development over the past three years. The rest of this paper is organized as follows. Section 2 describes the design flow of VLSI when HLS is used. Section 3 outlines the tasks and basic techniques. In Section 4, several new target architectures for HLS are surveyed. ....

P. Michel, U. Lauther, and P. Duzy, Editors, The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, Norwell, MA., 1992.

....Introduction The high level synthesis (HLS) task can be divided into three main subtasks; operation scheduling, resource allocation, and resource binding. Although these subtasks are interdependent most HLS systems solve them as separate problems to decrease the complexity of the algorithms [5] [8]. Furthermore, a fourth subtask is to decide the clock period for the design. This subtask is usually solved by the designer prior to HLS, if the clock period is not predetermined. The clock period is an important parameter of a digital design, since it has a large impact on the timing ....

P. Michel, U. Lauther, P. Duzy, "The Synthesis Approach to Digital Systems Design," Kluwer Academic Publishers, 1992.

....Department Technical University of Timisoara Romania 1 Dept. of Computer and Information Science Link ping University Sweden 1 1. Introduction Complex hardware circuits often require some timing restrictions to be incorporated in their behavioral specification for high level synthesis [6, 9]. These constraints have to be captured as part of the internal design representation generated after compilation of the input specification. Timing analysis has to be carried out in order to decide if the constraints are consistent, and operation scheduling is performed during synthesis according ....

P. Michel, U. Lauther, and P Duzy, The Synthesis Approach to Digital System Design (Kluwer Academic Publisher, 1992).

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P. Michel, U. Lauther, P. Duzy, "The Synthesis Approach To Digital System Design," Kluwer Academic Publishers, 1992

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P. Michel, U. Lauther, and P.Duzy, The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, 1992.

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P. Michel, U. Lauter, and P. Duzy, "The Synthesis Approach To Digital System Design", Kluwer Academic Publishers, 1992.

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