J. Hallberg and Z. Peng. Synthesis under local timing constraints in the CAMAD hig-level synthesis system. In IEEE EUROMICRO, Como, Italy, 1995. IEEE-Press. Home/Search Document Details and Download
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A Methodology for the Design of Guaranteed Correct .. - Middelhoek.. (1996) (2 citations) (Correct)
....proven correct. HYPER and TRADES are largely complementary. TRADES could use the automatic optimization algorithms developed for HYPER, while HYPER could benefit from our more powerful CDFG language, support for VHDL, and our much larger set of pre proven design transformations. The CAMAD system [Pen89, Pen94, HaP95] concentrates on automatic transformations for scheduling and allocation. For the automatic optimization of sparsely multiplexed data paths at the algorithmic level, the GATE tool [Jan94] has been developed at IMEC, Belgium. SynGuide [Sam93, Sam95] concentrates on both interactive and automatic ....
J. Hallberg, Z. Peng, Synthesis under Local Timing Constraints in the CAMAD High-Level Synthesis System, Proc. of IEEE EUROMICRO 95, pp. 650-655, Como, Italy, 1995.
From VHDL to Efficient and First-Time-Right Designs: A Formal.. - Middelhoek (1995) (5 citations) (Correct)
....automatic optimization algorithms developed for HYPER could be applied within TRADES while HYPER could benefit from our more powerful CDFG language, support for VHDL, and much larger set of pre proven design transformations which guarantees correctness by construction. The CAMAD [Pen89, Pen94, HaP95] high level synthesis system uses automatic transformations for scheduling and allocation. Algorithms written in Pascal or Behavioral VHDL used for specification are translated into an Extended Timed Petri Net representation in which data and control flow are separated. In comparison with TRADES ....
J. Hallberg, Z. Peng, Synthesis under Local Timing Constraints in the CAMAD High-Level Synthesis System, Proc. of IEEE EUROMICRO 95, Como, Italy, 1995.
High-Level Synthesis under Local Timing Constraints - Hallberg (1996) (1 citation) Self-citation (Peng) (Correct)
....quality of the results given by the high level synthesis process. 1.4 Contributions The work presented in this thesis makes several contributions to the area of high level synthesis. LTCs specified in behavioral VHDL are represented by addition of special arcs to the control part of the ETPN [Hal 95] The meaning of these special arcs in the ETPN is defined from the high level synthesis point of view. The LTCs are specified in real time values rather than in clock periods. Furthermore, the proposed scheduling techniques automatically selects the clock period for the design. Together this ....
....on the LSI 10K technology. 5.1 Motivation When the operations controlled by a place are assumed to be completed within a single clock period, the place whose operations have the longest execution delay will determine the minimal clock period of the design. This approach was used in chapter 4 and [Hal 95] In this chapter, however, it is assumed that the operations controlled by a place can use an arbitrary number of clock cycles to complete, that is, multicycle scheduling is performed. Since many designs contain operations with a wide spectrum of delays this approach allows implementations with ....
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J. Hallberg and Z. Peng, " Synthesis under Local Timing Constraints in the CAMAD High-Level Synthesis System," Proc. 21st EUROMICRO Conference, pp. 650-656, Como, Italy, Sep. 4-7, 1995.
Multicycle Scheduling under Local Timing Constraints using.. - Jonas Hallberg Self-citation (Hallberg Peng) (Correct)
....that the operations controlled by a place can use an arbitrary number of clock cycles to complete. Since many designs contain operations with a wide spectrum of delays this approach allows designs with a much better performance than a scheduling technique that only allows one clock cycle per place [5]. Each LTC in the design contains one or several paths of places. The delays of these sequences of places have to fulfill the corresponding LTC. Since the designs are synchronous the delay, D x , of a place P x is a multiple of the clock period, where T is the clock period of the design and d x ....
J. Hallberg and Z. Peng, "Synthesis under Local Timing Constraints in the CAMAD High-Level Synthesis System," Proc. 21st EUROMICRO Conference, pp. 650-656, Como, Italy, Sep. 4-7, 1995.
High-Level Synthesis Under Local Timing Constraints Using.. - Hallberg, Peng (1996) (1 citation) Self-citation (Hallberg Peng) (Correct)
....module allocation and binding algorithms were applied to the fifth order digital elliptic wave filter [11] and the 256 point Discrete Fourier Transform (DFT) 8] benchmarks the results in Table 4 and 5 were generated. These results are compared with those given by a unicycle scheduling technique [5], ARIEL [1] and the SALSA [10] HLS systems. As in the previous section, the used module library is based on the LSI 10K technology and the experiments have been carried out on a SPARCstation 10. The results in Table 4 have been produced assuming that the used multipliers have a delay which is ....
J. Hallberg and Z. Peng, "Synthesis under Local Timing Constraints in the CAMAD High-Level Synthesis System," Proc. 21st EUROMICRO Conf., pp. 650-656, 1995.
A Formal Approach to Specify and Synthesize at the System Level - Blumenröhr (Correct)
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J. Hallberg and Z. Peng. Synthesis under local timing constraints in the CAMAD hig-level synthesis system. In IEEE EUROMICRO, Como, Italy, 1995. IEEE-Press.
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