Altera Corporation, Altera Digital Library, June 2000.  Home/Search   Document Not in Database   Summary   Related Articles

....to use internal memory is to save logic cells to be used in the other parts of the JPEG compressor. XVI Microelectronics Seminar (a) b) Figure 4 a) example of a ping pong buffer; b) transpose buffer architecture The transpose buffer VHDL description is specific to be used with Altera [ALT 00] devices since internal FPGA memory are defined as Altera macroblocks. When the first 1 D DCT architecture writes the results line by line in one memory (RAM1 or RAM2) the second 1 D DCT architecture reads the input values column by column from the other memory (RAM2 or RAM1) The read (Rad ....

....generated by a control block and this control block defines, by Control signal in Fig. 4 b) which memory is used to Read Write at each memory access step. 3. VHDL Synthesis Results The 2 D DCT architecture was described in VHDL. This VHDL was synthesized into an Altera Flex 10KE family FPGA [ALT 00] The VHDL description of the two 1D DCT architectures is structural and device independent. This VHDL can be used for FPGAs or standard cell synthesis approach. The VHDL of the transpose buffer uses an Altera specific library that allows the use of internal memory, making it an Altera dependent ....

Altera Corporation, Altera Digital Library, June 2000.

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