P. Gibbons and M. Merritt. Specifying non-blocking shared memories. In Proc. Fourth ACM Symp. on Parallel Algorithms and Architectures, pages 306--315, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....programmability for performance. Sequential consistency was first defined by Lamport [19] in this paper, we use an alternative formulation proposed by Afek et al. 2] based on I O automata. Other papers exploring correctness conditions for shared memory and algorithms that implement them include [1, 3, 5, 8, 9, 11, 12, 13, 14, 15, 16, 21, 24]. In most of this work, memory is modeled as a collection of items that are accessed through read and write operations. The study of correctness for shared memory with more general data types was initiated by Herlihy and Wing [17] Sequential consistency and other consistency conditions for ....

P. Gibbons and M. Merritt. Specifying non-blocking shared memories. In Proc. Fourth ACM Symp. on Parallel Algorithms and Architectures, pages 306--315, 1992.

....programmability for performance. Sequential consistency was first defined by Lamport [19] in this paper, we use an alternative formulation proposed by Afek et al. 2] based on I O automata. Other papers exploring correctness conditions for shared memory and algorithms that implement them include [1, 3, 5, 8, 9, 11, 12, 13, 14, 15, 16, 21, 24]. In most of this work, memory is modeled as a collection of items that are accessed through read and write operations. The study of correctness for shared memory with more general data types was initiated by Herlihy and Wing [17] Sequential consistency and other consistency conditions for ....

P. Gibbons and M. Merritt. Specifying non-blocking shared memories. In Proc. Fourth ACM Symp. on Parallel Algorithms and Architectures, pages 306--315, 1992.

....(e.g. those allowed by more relaxed consistency models) We build on a large body of previous work that has used such a programmer based approach. In particular, several papers have been published to determine the information needed to exploit optimizations of current relaxed consistency models [1, 5, 6, 9, 10, 20, 22, 18, 23, 24, 30]. However, the process of determining such information has been mostly ad hoc, and does not provide insight into information that can be used for other future optimizations. Further, the proofs that the information is correct are fairly complex [6, 7, 9, 10, 22, 23, 24, 30] and or prohibit common ....

....models [1, 5, 6, 9, 10, 20, 22, 18, 23, 24, 30] However, the process of determining such information has been mostly ad hoc, and does not provide insight into information that can be used for other future optimizations. Further, the proofs that the information is correct are fairly complex [6, 7, 9, 10, 22, 23, 24, 30] and or prohibit common processor behavior (e.g. some work [9, 10, 23, 24, 30] prohibits true speculative execution as implemented in many current and next generation processors) In contrast to the ad hoc nature of previous applications of the programmer based approach, this paper describes a ....

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P. B. Gibbons and M. Merritt. Specifying Nonblocking Shared Memories. In Proc. Symp. on Parallel Algorithms and Architectures, pages 306--315, 1992.

....a given execution is sequentially consistent. The need for formal frameworks for memory models has been felt by other researchers. Gibbons, Merrit, and Gharachorloo [67] use the I O automata model of Lynch and Tuttle [105] to give a formal specification of release consistency [64] Later work [66] extends the framework to nonblocking memories. The main concern of these papers is to expose the architectural assumptions that are implicit in previous literature on relaxed memory models. In this chapter, rather than focusing on the correctness of specific implementations of a memory model, we ....

P. B. GIBBONS AND M. MERRITT, Specifying nonblocking shared memories, in Proceedings of the Fourth Annual ACM Symposium on Parallel Algorithms and Architectures, 1992, pp. 306--315.

....programmability for performance. Sequential consistency was first defined by Lamport [20] in this paper, we use an alternative formulation proposed by Afek et al. 2] based on I O automata. Other papers exploring correctness conditions for shared memory and algorithms that implement them include [1, 3, 5, 8, 9, 11, 12, 13, 15, 16, 17, 21, 24]. In most of this work, memory is modeled as a collection of items that are accessed through read and write operations. The study of correctness for shared memory with more general data types was initiated by Herlihy and Wing [18] Sequential consistency and other consistency conditions for ....

P. Gibbons and M. Merritt. Specifying non-blocking shared memories. In Proc. Fourth ACM Symp. on Parallel Algorithms and Architectures, pages 306-- 315, 1992.

....is sequentially consistent. The need for formal frameworks for memory models has been felt by other researchers. Gibbons, Merrit, and Gharachorloo [GMG91] use the I O automata model of Lynch and Tuttle [LT87] to give a formal specification of release consistency [GLL 90] Later work [GM92] extends the framework to nonblocking memories. The main concern of these papers is to expose the architectural assumptions that are implicit in previous literature on relaxed memory models. In the present paper, rather than focusing on the correctness of specific implementations of a memory ....

Phillip B. Gibbons and Michael Merritt. Specifying nonblocking shared memories. In Proceedings of the Fourth Annual ACM Symposium on Parallel Algorithms and Architectures, pages 306--315, 1992.

....orders the operations of each processor. The DASH implementation of processor consistency uses a partial program order (see Section 5. 2 below) In addition, there has been recent interest in the formalization of systems with non blocking reads, in which the order of local operations may be partial [13]. 2 It is assumed that each location has some initial value that is returned by a read of a location with no preceding write. The Power of Processor Consistency 5 p: w(x)0 w(x)1 r(y)0 q: w(y)0 w(y)1 r(x)0 Figure 1: A history that is not sequentially consistent be seen in the order in which ....

....Our method is history based ; it defines a memory model by comparing its executions to those of an ideal serial memory. While this technique has been used by other researchers to define shared memories [5,16,21,24] it has never been used to define processor consistency. Other researchers [13,14] have used a formal automaton based method for defining shared memories. We have also used this method to define another shared memory, called causal memory [2] Like processor consistency, causal memory lies between between PRAM and sequential consistency in a hierarchy of shared memories. ....

Phillip B. Gibbons and Michael Merritt. Specifying nonblocking shared memories (extended abstract). In Proceedings of the Fourth Symposium on Parallel Algorithms and Architectures, pages 306--315. ACM Press, June 1992.

....a large selection of memory consistency models. Most closely related to our research are several papers presenting formal descriptions of specific memory models [22, 2, 1, 4, 5, 8, 14, 13, 16, 20, 27, 30] and papers that present various formalisms for describing memories and reasoning about them [3, 6, 7, 4, 11, 15, 25, 26, 17, 29, 33]. Our work has benefited from all of these papers. For an extensive bibliography on memory consistency models see the online listing at the University of Alberta (http: www.cs.ualberta.ca rasit dsmbiblio node2.html) Section 2 reviews a framework for defining memory consistency models, and then ....

P. B. Gibbons and M. Merritt. Specifying nonblocking shared memories. In Proc. 4th ACM Symp. on Parallel Algorithms and Architectures, pages 306--315, 1992.

....that a given execution is sequentially consistent. The need for formal frameworks for memory models has been felt by other researchers. Gibbons, Merrit, and Gharachorloo [67] use the I O automata model of Lynch and Tuttle [105] to give a formal specification of release consistency [64] Later work [66] extends the framework to nonblocking memories. The main concern of these papers is to expose the architectural assumptions that are implicit in previous literature on relaxed memory models. In this chapter, rather than focusing on the correctness of specific implementations of a memory model, we ....

P. B. GIBBONS AND M. MERRITT, Specifying nonblocking shared memories, in Proceedings of the Fourth Annual ACM Symposium on Parallel Algorithms and Architectures, 1992, pp. 306--315.

....programmability for performance. Sequential consistency was first defined by Lamport [26] in this paper, we use an alternative formulation proposed by Afek et al. 4] based on I O automata. Other papers exploring correctness conditions for shared memory and algorithms that implement them include [2, 3, 5, 11, 12, 15, 17, 18, 19, 20, 21, 28, 33]. A valuable survey of these ideas is given by Adve and Gharachorloo [1] In most of previous work, memory is modelled as a collection of items that are accessed through read and write operations. The study of correctness for shared memory with more general data types was initiated by Herlihy ....

....in execution; as a result, the Orca implementation has been modified to correct this error. This work opens up many avenues for future research. First, some simple extensions to our results can be made. For example, we could allow concurrent invocations of operations by the same client, as in [20], instead of requiring clients to block. In order to handle this case, we need to adjust our definition of sequential consistency to eliminate the client well formedness condition, to modify the algorithm to maintain sets of active operations, and to make minor changes in our proofs. Another ....

P. Gibbons and M. Merritt. Specifying non-blocking shared memories. In Proc. Fourth ACM Symp. on Parallel Algorithms and Architectures, pages 306--315, 1992.

....violating sequential consistency. We build on a large body of previous work that has used such a programmer based approach. In particular, several papers have been published (by us and others) to determine the information needed to exploit optimizations of current relaxed consistency models [1, 6, 7, 12, 13, 24, 28, 29, 30, 42]. However, the process of determining such information has been mostly ad hoc, and does not provide insight into information that can be used for other future optimizations. Further, the proofs that the information is correct are fairly complex [7, 8, 12, 13, 28, 29, 30, 42] and or prohibit common ....

....models [1, 6, 7, 12, 13, 24, 28, 29, 30, 42] However, the process of determining such information has been mostly ad hoc, and does not provide insight into information that can be used for other future optimizations. Further, the proofs that the information is correct are fairly complex [7, 8, 12, 13, 28, 29, 30, 42] and or prohibit common processor behavior (e.g. some studies [12, 13, 29, 30, 42] prohibit true speculative execution as implemented in many current and next generation processors) In contrast to the ad hoc nature of previous applications of the programmer based approach, this paper describes a ....

[Article contains additional citation context not shown here]

P. B. Gibbons and M. Merritt. Specifying Nonblocking Shared Memories. In Proc. Symp. on Parallel Algorithms and Architectures, pages 306--315, 1992.

....Discussion We have presented a technique to define non atomic memories in terms of atomic operations. Our approach is useful for the understanding and comparison of non atomic memories and for the verification of parallel algorithms that use these memories. In a related work, Gibbons and Merritt [8] outline a framework for specifying non blocking shared memories based on I O automata [13] and use it to specify release consistency [7] In the future, we intend to develop specifications for other existing consistency conditions as well as investigate semantic constraints under which atomic ....

P. B. Gibbons and M. Merritt. Specifying nonblocking shared memories. In Proceedings of the Fourth Annual ACM Symposium on Parallel Algorithms and Architectures, 1992.

....and it is easier to transform a serial program into a distributed shared memory based program, than to a message passing based program. For these reasons and others, much research has been done on how to define and implement distributed shared memory, both from the theoretical point of view [2, 3, 6, 10, 11, 13, 22, 26, 27, 28] and from the practical point of view [14, 17, 18, 19, 21, 31, 32, 33] However, most of this work ignores the possibility of failures and does not allow processors to join an ongoing computation, in order to speed it up. On the other hand, it is clear that if distributed shared memory is to be ....

P. Gibbons and M. Merritt. Specifying Non-Blocking Shared Memories. In Proc. 4th ACM Symp. on Parallel Algorithms and Architectures, pages 306--315, July 1992.

....o p;j in the program, i.e. i j. In this case, we say o p;i is ordered 4 before o p;j by the program order. This defines program order to be total on any processor execution history; it orders all operations of a given processor. Some memory definitions consider non blocking operations [7]; after invoking a non blocking operation. When considering such operations, an operation o p;i 1 that follows o p;i may bypass it. In other words, o p;i 1 may complete before o p;i in some processor view. In this case, all orderings defined by po may not be maintained. Thus, in such systems ....

Phillip B. Gibbons and Michael Merritt. Specifying nonblocking shared memories (extended abstract). In Proceedings of the Fourth Symposium on Parallel Algorithms and Architectures, pages 306--315. ACM Press, June 1992.

....by the general method. 1.3 Related Work Our work joins two previous works in attempting to provide a formal memory model for an existing architecture and using this model to develop programming techniques for systems based on this architecture. The first is for the Stanford DASH multiprocessor [19, 20] and the second is for PowerPC based multiprocessors [12] Gharachorloo, Gibbons and Merritt define release consistency, a formal definition of the memory model of the Stanford DASH multiprocessor. They show that PL programs run on release consistency as if it was sequentially consistent [19, 20] ....

....[19, 20] and the second is for PowerPC based multiprocessors [12] Gharachorloo, Gibbons and Merritt define release consistency, a formal definition of the memory model of the Stanford DASH multiprocessor. They show that PL programs run on release consistency as if it was sequentially consistent [19, 20]. PL programs are similar to generalized data race free programs. There is a slight difference between the way release and acquire operations and the interaction between them are defined in alpha consistency and in release consistency. In alpha consistency, release and acquire are sequences of ....

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P. Gibbons and M. Merritt. Specifying Non-Blocking Shared Memories. In Proc. 4th ACM Symp. on Parallel Algorithms and Architectures, pages 306--315, July 1992.

....for the relatively complete implementation, yields the desired correctness proof. Behavior inclusion can be proved using the theory of trace inclusion [21] for I O automata [20] which develops refinements and forward and backward simulations as proof tools. In related work, Gibbons and Merritt [11] use I O automata to define a base memory system supporting per variable consistency, or cache consistency. The actions of this automaton are later restricted to support release consistency [10] They establish that release consistency behaves as sequential consistency in the absence of data ....

Gibbons, P. B., and Merritt, M. Specifying nonblocking shared memories. In SPAA '92 (San Diego, CA, USA, 29 June--1 July 1992), pp. 306--15.

....release consistency and entry consistency for Midway [BZS92] The specification of entry consistency, however, seems to be incomplete; Chapter 7 discusses this issue further. Gibbons and Merritt have proposed a relaxation of release consistency (RCsc) that is a generalization of entry consistency [GiM92]. This relaxation allows a programmer to associate a release with a subset of the preceding operations. A release now needs to wait for only its associated data operations (and all preceding synchronization operations) to be performed. Gibbons and Merritt state and prove the correctness of a ....

....all memory operations, where the order obeys certain axioms [SUN91, SFC91] The advantage of this formalism is that it captures the write buffer interaction described above; the disadvantage, however, is that it does not adequately model the non atomicity of writes. Gibbons et al. and Afek et al. [ABM89,ABM93,GMG91, GiM92] use the formalism of an I O automaton developed by Lynch and Tuttle [LyT88] This formalism expresses the system in terms of a non deterministic automaton. The formalism is powerful and precise, and does not suffer from the disadvantages of the above formalisms. However, compared to other ....

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P. B. GIBBONS and M. MERRITT, Specifying Nonblocking Shared Memories, Proc. Symp. on Parallel Algorithms and Architectures, 1992, 306-315.

....has been the absence of a clear semantics. To circumvent this problem, we define the mixed consistency model formally by identifying a clear interface between the user programs and the memory system. This model is presented in Section 3 and is general enough to permit non blocking operations [15] and multi threaded user processes. We also develop conditions under which programming in our model has the same final effect as that of using sequentially consistent memory. Such conditions can be useful for a programmer and also for a compiler, which can exploit these conditions to speed up a ....

....and the execution of any access cannot complete before all preceding acquire operations have completed. Based on the above classification scheme, they propose a new correctness condition called release consistency that permits greater concurrency than before. More recently, Gibbons and Merritt [15] have presented a generalization of release consistency in which shared accesses are non blocking. Release consistency, though originally proposed for the DASH architecture [21] has also been adopted in software implementations of DSM. In these systems, explicit lock and unlock operations play ....

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Phillip B. Gibbons and Michael Merritt. Specifying nonblocking shared memories. In Proceedings of the 4th Annual ACM Symposium on Parallel Algorithms and Architectures, pages 306--315, 1992.

....a collection of accesses. In the qrqw asynchronous pram, pipelining of memory accesses is permitted; a processor may have multiple shared memory operations in progress at a time. A formal definition of a sequentially consistent shared memory that permits pipelining is given by Gibbons and Merritt [GM92] Each processor has a private local memory, and the following types of instructions: local operations, shared memory reads, shared memory writes, and shared memory Test Set operations. A Test Set operation reads and returns the old value and writes a 1; the location is assumed to be initialized ....

....of a collection of processors operating asynchronously and communicating via a global shared memory. The shared memory is sequentially consistent and supports the pipelining of memory requests by processors (i.e. each processor is permitted to have multiple pending shared memory requests; see [GM92] for a formal definition) Each processor has a private local memory, and the following types of instructions: RAM operations involving only its private state and private memory, requests to read the contents of a shared memory location into a private memory location, requests to write the ....

P. B. Gibbons and M. Merritt. Specifying nonblocking shared memories. In Proc. 4th ACM Symp. on Parallel Algorithms and Architectures, pages 306--315, June-July 1992.

.... consistency within the memory system itself [14, 15] work on testing the serializability of database transactions [31] work on detecting data races (e.g. 2, 23, 28, 29] work on proving that weak memory systems provide sequential consistency for programs that are free of data races (e.g. [1, 20, 21]) work on testing uniprocessor memories [9] work on algorithms for testing data structures on uniprocessors (e.g. 10] work on verifying specific properties of cache coherence protocols (e.g. 32] and the references therein) work on computing with faulty shared memories [4] work on ....

P. B. Gibbons and M. Merritt, Specifying nonblocking shared memories, in Proc. 4th ACM Symp. on Parallel Algorithms and Architectures, June-July 1992, pp. 306--315.

....shared memory requests and continue without waiting for them to complete (pipelining) However, the first subsequent RAM operation that uses the result of such a shared memory request will wait for the value to be returned. The global memory is a sequentially consistent nonblocking shared memory [GM92] as follows. Each processor issues shared memory requests (read, write, test set) one at a time. There is a partial order on the requests by a processor, called the local order for that processor. The memory system appears (for the purpose of correctness) to be a serial memory that processes one ....

P. B. Gibbons and M. Merritt. Specifying nonblocking shared memories. In Proc. 4th ACM Symp. on Parallel Algorithms and Architectures, pages 306--315, June-July 1992.

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