Jai Rawat. Static analysis of cache performance for real-time programming. Master thesis TR93-19, Iowa State University of Science and Technology, November 17, 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....cache and pipeline performance. 2.1.2 Static analysis Static analysis means that the software is examined without being executed. For instance, there are several approaches that are based on integer linear programming [LM95, OS97] data flow analysis [AMWH94, LML 94] graph coloring [Raw93], abstract interpretation [AM95, FMWA99] and reducing [NR95, LS99b, SA97, TD00] among others. To keep things brief, only two of these methods have been chosen to illustrate what static analysis is all about. This method was developed at Florida state university and is often referred as ....

Jai Rawat. Static analysis of cache performance for real-time programming. Master thesis TR93-19, Iowa State University of Science and Technology, November 17, 1993.

....intermixing was done in [7] by borrowing a data distribution function from parallel computing and a posteriori evaluation through a cost function, whereas the present approach allows more systematic intermixing. Graph coloring wrt. caches was examined in the context of cache analysis by Rawat [17]. He contributes to the notion of togetherness of values in a cache line. Coloring as a heuristic is more appropriate for optimization. By not taking reuse information into account, the estimates made by Rawat overestimate cache misses signi cantly. Hashemi, Kaeli and Calder [9] applied a coloring ....

Jai Rawat. Static analysis of cache performance for real-time programming. Technical Report IASTATECS//TR93-19, Iowa state university, Nov 1993.

....lower than theirs. Moreover, strictly speaking, the notion of locality applies to fully associative caches only. The more realistic case of low associativity caches is not considered there. The combination of values into cache lines was examined in the context of cache analysis by Rawat [Raw93]. By not taking reuse information into consideration, the estimations made by Rawat s method are too coarse and often overestimate cache misses significantly. Panda, Nicolau et al. PNDN97] show a simple but striking approach to the problem of conflict misses in data caches which might provide an ....

Jai Rawat. Static analysis of cache performance for real-time programming. Technical Report IASTATECS//TR93-19, Iowa state university, November 19 1993.

....5 how the meeting graph is applied. Section 6 shows the application of the result to actual memory layout. Results of measurements can be found in Section 7. We conclude by outlining further work. 2 Related work Graph coloring wrt. caches was examined in the context of cache analysis by Rawat [Raw93] He contributes the notion of togetherness of values in a cache line. Coloring as a heuristic is more appropriate for optimization. By not taking reuse information into account, the estimations made by Rawat overestimate cache misses significantly. Hashemi, Kaeli and Calder [HKC97] applied a ....

Jai Rawat. Static analysis of cache performance for real-time programming. Technical Report IASTATECS//TR93-19, Iowa state university, Nov 1993. REFERENCES 32

....in the order of priorities that depends on anticipated performance speedup. The remaining variables that are uncolored (maybe even uncolorable) must share registers and therefore leverages are split and new graphs created. Jai Rawat A master thesis from Iowa state university by Jai Rawat[Raw93] describes a static analysis method to find intrinsic misses in a direct mapped data cache memory. Rawat s technique for static analysis of cache behavior is similar to Chow and Hennessy s register allocation. The (data) cache block contains variables from where live ranges are specified. These ....

.... # # Lim S S et al. 94 95 # # # # # # # # # Lin Liou 1991 # # # Liu Lee 1994 # # # Lundqvist Stenstrm 1999 # # # # # # # Mueller 1995 # # # # Mulleret al.. 1998 # # # # # Nilsen Rygg 1995 # # # # Ottosson Sjdin 1997 # # # # # # # # Petters Frber 1999 # # # # # # # # # # # # # # Rawat 1993 # # # # Strner 1998 # # # # # Theiling Ferdinand 98 00 # # # # # # # # Tomiyama Dutt 2000 # # # Wolfe 1993 # # Chapter 4 Conclusions This chapter summarizes and discusses the state of the art in the area of real time systems and with focus on cache memories. 4.1 Summary 4.1.1 ....

Jai Rawat. Static analysis of cache performance for real-time programming. Master thesis TR93-19, Iowa State University of Science and Technology, November 17, 1993.

....exactly describe the data and control flow behavior of programs which among others enables precise modeling of loops. In (Theiling and Ferdinand, 1998) IPET was enriched with information of the abstract interpretation described in (Alt et al. 1996) A graph coloring approach is used in (Rawat, 1993) to estimate the number of cache misses for real time programs. The approach only supports data caches with random replacement strategy 7 . It employs standard data flow analysis and requires compiler support for placing variables in memory according to the results of the presented algorithm. ....

Rawat, J.: 1993, `Static Analysis of Cache Performance for Real-Time Programming '. Master's thesis, Iowa State University of Science and Technology, Dept. of Computer Science.

....have been reported in [McFarling 1989; Tomiyama and Yasuura 1996] Li et al. 1995] present a technique for estimation of instruction cache performance. De Greef et al. 1995] have studied the effect of cache parameters and memory organization strategies on video and imaging applications. Rawat [1993] and Austin [1996] have addressed the problem of variable placement for improving cache performance. However, Rawat addresses only scalar variables, and Austin treats scalar and array variables alike, thereby missing array placement opportunities based on their index expressions. In comparison, we ....

Rawat, J. 1993. Static analysis of cache performance for real-time programming, Iowa State University.

....the total execution time of an embedded application by a careful partitioning of scalar and array variables used in the application into off chip DRAM (accessed through data cache) and Scratch Pad SRAM. Optimization techniques for improving the data cache performance of programs have been reported [4, 7, 9]. The analysis in [9] is limited to scalars, and hence, not generally applicable. Iteration space blocking for improving data locality is studied in [4] This technique is also limited to the type of code that yields naturally to blocking. In [7] a data layout strategy for avoiding conflict ....

....an embedded application by a careful partitioning of scalar and array variables used in the application into off chip DRAM (accessed through data cache) and Scratch Pad SRAM. Optimization techniques for improving the data cache performance of programs have been reported [4, 7, 9] The analysis in [9] is limited to scalars, and hence, not generally applicable. Iteration space blocking for improving data locality is studied in [4] This technique is also limited to the type of code that yields naturally to blocking. In [7] a data layout strategy for avoiding conflict misses is presented. ....

J. Rawat, "Static analysis of cache performance for realtime programming," Masters thesis, Iowa State University, May 1993.

....for cache and pipeline behavior, described below, have both been influenced by this basic paradigm. 4. Static Prediction of Cache Performance In previously reported research, we have studied analysis techniques to statically distinguish instructions that hit the cache from those that don t [2, 19]. The general technique is to compute a live range that represents the set of blocks during which certain information is known to reside within the cache. Within each function s control flow graph, a variable s live range begins with nodes that first reference the variable and ends with nodes ....

....that determining worst case execution paths for the targeted computing environments was not at all straightforward. And this paper summarizes our experience. Most of the other research that has been published to date focuses on only one aspect of the more complete problem. For example, references [1 3, 6 9, 11 13, 19, 23] discuss techniques for analyzing cache performance. Pipeline analysis for real time predictability has been reported in [4, 5, 10, 22, 24] To our knowledge, the only other paper to consider the relationships between programming and analysis techniques is [15] 8. Acknowledgments We thank the ....

J. Rawat, Static Analysis of Cache Performance for Real-Time Programming, Iowa State Univ. Tech. Rep. 93-19, Master's Thesis, Iowa State Univ., 1993.

....even worse than the ones without data cache analysis. This is later improved in the work by Kim et al. 5] who use linear Diophantine equations to analyze nested loops. The limitation of this method is that the memory accessed within the loop body must be fit entirely into the data cache. Rawat [9] used graph coloring techniques to analyze data cache performance. This approach has limited success even for small programs. In this paper we handle the complex extensions of our previous work to handle set associative caches, data caches and unified caches. We will briefly describe the direct ....

J. Rawat. Static analysis of cache performance for real-time programming. Master's thesis, Iowa State University of Science and Technology, November 1993. TR93-19.

....a timing estimation for real time systems since their predictions are usually not guaranteed, or enormous cost is needed. Because of these limitations of the measurementbased approaches, analytical approaches are becoming more popular. There have been several recent studies about this issue [4, 8, 9, 18, 19, 20, 22, 23, 24, 27, 28]. In many of these studies, the assumed machine model is a simple non pipelined processor without cache memory [18, 22, 23, 27] Thus the timing effects of pipelined execution and cache memory are not taken into account. 2.1 Timing analysis of pipelined execution The timing effects of pipelined ....

....avoided if the cache has a limited size and or set associativity. Among the analytical WCET prediction schemes that we are aware of, only three schemes take into account the timing variation resulting from intra task cache interference (two for instruction caches [19, 21] and one for data caches [24]) The static cache simulation approach which statically predicts hits or misses of instruction references is due to Mueller, Whalley and Harmon [19] In this approach, instructions are classified into the following four categories based on a data flow analysis: ffl always hit: The instruction is ....

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J. Rawat. Static Analysis of Cache Performance for Real-Time Programming. Master's thesis, Iowa State University, 1993.

....used to obtain such bounds. Measurement based techniques are, in many cases, inadequate to produce a timing estimation for real time systems since their predictions are usually not guaranteed, or enormous cost is needed. Due to these limitations, analytical approaches are becoming more popular [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]. Many of these analytical studies, however, consider a simple machine model, thus largely ignoring the timing effects of pipelined execution and cache memory [8, 12, 13, 15] A. Timing Analysis of Pipelined Execution The timing effects of pipelined execution have been recently studied by Harmon, ....

....if the cache has a limited size and or set associativity. Among the analytical WCET prediction schemes that we are aware of, only four schemes take into account the timing variation resulting from intra task cache interference (three for instruction caches [10, 9, 7] and one for data caches [14]) The static cache simulation approach which statically predicts hits or misses of instruction references is due to Arnold, Mueller, Whalley and Harmon [10] In this approach, instructions are classified into the following four categories based on a data flow analysis: ffl always hit: The ....

[Article contains additional citation context not shown here]

J. Rawat, "Static Analysis of Cache Performance for Real-Time Programming," Master's thesis, Iowa State University, 1993.

....control the memory mapping. Moreover, strictly speaking, the notion of locality applies to fully associative caches only. The more realistic case of low associativity caches is not considered there. The combination of values into cache lines was examined in the context of cache analysis by Rawat [Raw93]. By not taking reuse information into consideration, the estimations made by Rawat s method are too coarse and often overestimate cache misses significantly. Panda, Nicolau et al. PNDN97] show a simple but striking approach to the problem of conflict misses in data caches: useless data is ....

Jai Rawat. Static analysis of cache performance for real-time programming. Technical Report IASTATECS//TR93-19, Iowa state university, November 19 1993.

....system dependent, and delimits the conditions where each policy works well. 2 Related Work Much of the research in real time predictable cache behavior has focussed on analyzing an application s behavior with respect to a uniprocess system that does not suffer interprocess contention for the cache [13, 10, 14, 7, 5]. For a multitasking environment, two basic methods have been proposed for controlling interprocess cache interference for predictable cache behavior. The first method relies on dividing the cache into distinct partitions and the other restricts where context switches can occur. Kirk and ....

Jai Rawat. Static Analysis of Cache Performance for Real-Time Programming. Technical Report TR93-19, Iowa State University of Science and Technology, November 1993.

....limited. Arnold et al. 8] propose a less aggressive cache analysis method. They use flow analysis to identify the potential cache conflicts and classify each instruction as first miss, always hit, always miss or first hit categories. This results in fast but less accurate cache analysis. Rawat [9] handles data cache performance analysis by using graph coloring techniques. However, this approach has limited success even for small programs. A severe drawback of all the above methods is that they cannot handle any user annotations describing infeasible program paths, which are essential in ....

Jai Rawat, "Static analysis of cache performance for real-time programming", Master's thesis, Iowa State University of Science and Technology, November 1993, TR93-19.

....be avoided if the cache has a limited size and or set associativity 3 and make it difficult to accurately predict the WCET of a task due to the cyclic dependency explained earlier. Recently substantial progress has been made in this area and interested readers are referred to [2] 16] 17] [19]. Inter task interference is caused by task preemption. When a task is preempted, most of its cache blocks are displaced by the newly scheduled task and the tasks scheduled thereafter. When the preempted task resumes execution, it requests the previously displaced blocks and experiences a burst of ....

J. Rawat. Static Analysis of Cache Performance for Real-Time Programming. Master's thesis, Iowa State University, 1993.

....Arnold et al. 6] propose a less ag gressive cache analysis method. They use flow analysis to identify the potential cache conflicts and classify each instruction as first miss, always hit, always miss or first hit categories. This results in fast but less accurate cache analysis. Rawat [7] handles data cache performance analysis by using graph coloring techniques. However, this approach has limited success even for small programs. All the above methods encounter computational complexity because they try to determine the exact sequence of cache hits and misses. Different pessimistic ....

Jai Rawat, "Static analysis of cache performance for realtime programming", Master's thesis, Iowa State University of Science and Technology, November 1993, TR93-19.

....30 as instruction cache misses. Referring to the graph in figure 1 a 30 miss rate shows that estimates of best case to worst case differ by a factor of 7.0 assuming a 20 cycle miss penalty. Data loads can also be a source of large variability. Work in predicting the hit rates in the data cache [15, 2] have not been nearly as successful as similar work for instruction references. Experimental results have shown miss rate predictions ranging from 30 up to 100 for applications with very low actual miss rates. Because of the large variance we shall assume a 100 miss rate in the WCET. From the ....

Jai Rawat. Static Analysis of Cache Performance for Real-Time Programming. Technical Report TR93-19, Iowa State University of Science and Technology, November 1993.

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