A. Orairoglu, R. Karri: "Automatic Synthesis of SelfRecovering VLSI Systems", IEEE Trans. Comp., vol. 45, n. 2, Feb. 1996, pp. 131-142  Home/Search   Document Not in Database   Summary   Related Articles   Check

....applications that do incur faults. A substantial amount of research has been committed to increase reliability at various design levels, from the microarchitecture [1] to the system level [2] CAD synthesis and hardware design techniques have been proposed that focus on enhancing reliability [3] [4]. FPGA are commonly incorporated into systems requiring high reliability. Therefore, a low overhead fault recovery algorithm has been developed for FPGA that can recover from faults at runtime with minimal system downtime and no end user CAD tool requirements. The approach takes advantage of the ....

A. Orailoglu and R. Karri, "Automatic synthesis of self-recovering VLSI systems," IEEE Trans. Computers, vol. 45, no. 2, pp. 131--142, Feb. 1996.

....and testability. Relatively little work has been reported on behavioral level synthesis techniques for fault tolerant design. Raghavendra and Lursinsap [18] concentrated on designs with self recovery from transient faults using micro roll back and checkpoint insertion. Karri and Orailoglu [7] 8] [14] develop a spectrum of behavioral techniques which minimize the fault tolerance overhead in application specific designs. Recently, Iyer et al. 6] develop 5 a high level synthesis approach to optimize manufacturability using redundant interconnects. Guerra et al. 5] develop a heterogeneous BISR ....

A. Orailoglu, R. Karri, "Automatic Synthesis of Self-Recovering VLSI Systems," IEEE Trans. on Computers, Vol. 45, No. 2, pp. 131-142, 1996. 16

....is moving towards deeper submicron integration and reduced power supply voltages. These make systems more susceptible to physical failures and increase the need for on line testing [6] With the addition of self recovering or self repair techniques, extremely robust systems can be produced [8]. High level (or behavioural) synthesis [9] provides a designer with the capability to consider several realisations of a conceptual design, in a fast and efficient manner. In this way, the designer can estimate the characteristics (area, performance, testability, power dissipation) of each ....

....introduced multiplexer) Similarly, we can duplicate 2 and 3 during cs 3, binding the duplicate operations to modules A2 and A1 respectively. This way, we duplicate operations (as opposed to operators) saving hardware. Two recent examples of algorithmic duplication techniques are presented in [3,8]. In [8] algorithmic duplication is combined with rollback to provide error recovery, while in [3] module differentiation is exploited to provide fault identification. Having demonstrated the scope for hardware savings that algorithmic duplication introduces, it is this particular form of ....

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A. Orailoglu, R. Karri, "Automatic Synthesis of Self-Recovering VLSI Systems", IEEE Transactions on Computers, Vol. 45, No. 2, February 1996, p. 131-142.

....has been addressing synthesis and optimization of a single CDFG for sampling rate, area, and more recently power and test hardware overhead minimization [8, 15] Recently, a few efforts have been reported on behavioral synthesis techniques for fault tolerant designs. Karri and Orailoglu [5] presented scheduling, assignment and transformation based methods for fault tolerance against transient faults. Guerra et al. 3] presented the first work which concentrates on permanent faults. They showed how fault tolerance achieved using a set of spare units can be used for yield and ....

A. Orailoglu and R. Karri, "Automatic Synthesis of Self-Recovering VLSI Systems, " IEEE Trans on Computers, February 1996.

....the problem, and present extensive experimental results. Finally, we conclude our contribution in Section VI. II. Previous Work Recently, algorithm selection has been recognized as an important system level synthesis topic, and several approaches have been proposed [9] Karri and Orailoglu [4] [8] develop a spectrum of behavioral techniques which minimize the fault tolerance overhead in application specific designs. Recently,Iyer et al. 3]develop a high level synthesis approach to optimize manufacturability using redundantinterconnects. Guerra et al. 2] develop a heterogeneous BISR ....

A. Orailoglu, R. Karri, "Automatic Synthesis of SelfRecovering VLSI Systems," IEEE Trans. on Computers, Vol. 45, No. 2, pp. 131-142, 1996.

....design problem requires sophisticated planning in both operation scheduling and hardware binding, and these tasks fall squarely within the problem domain of high level synthesis. In fact, high level synthesis of fault tolerant designs has been investigated and implemented in [3] 7] and [8]. Moreover, the procedural approaches in high level # This work is supported by the National Science Foundation under grant number MIP 9308535. synthesis advocate a systematic definition of the underlying architecture, which in turn assists efficient planning of reconfigurable system designs. ....

A. Orailoglu and R. Karri. Automatic Synthesis of SelfRecovering VLSI Systems. IEEETransactions on Computers, February 1996.

....and testability. Relatively little work has been reported on behavioral level synthesis techniques for fault tolerant design. Raghavendra and Lursinsap [17] concentrated on designs with self recovery from transient faults using micro roll back and checkpoint insertion. Karri and Orailoglu [6] 7] [13] develop a spectrum of behavioral techniques which minimize the fault tolerance overhead in application specific designs. Recently, Iyer et al. 5] develop a high level synthesis approach to optimize manufacturability using redundant interconnects. Guerra et al. 4] develop a heterogeneous BISR ....

A. Orailoglu, R. Karri, "Automatic Synthesis of Self-Recovering VLSI Systems," IEEE Trans. on Computers, Vol. 45, No. 2, pp. 131-142, 1996.

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A. Orairoglu, R. Karri: "Automatic Synthesis of SelfRecovering VLSI Systems", IEEE Trans. Comp., vol. 45, n. 2, Feb. 1996, pp. 131-142

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A. Orailoglu, R. Karri, "Automatic Synthesis of SelfRecovering VLSI Systems", IEEE Transactions on Computers, Vol. 45, No. 2, February 1996, p. 131-142.

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