L. Whetsel, "Adapting Scan Architectures for Low Power Operation ", in ITC, pp. 863--872, 2000. Home/Search Document Not in Database Summary Related Articles Check |
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Controlling Peak Power during Scan Testing - Sankaralingam, Touba (2002) (1 citation) (Correct)
....will not help with peak power problems during the capture cycle (which can arise if the circuit is placed in a state that it could not be in during functional operation) A drawback of this approach is that it degrades circuit performance because it adds extra logic in the functional paths. In [Whetsel 00] an adapted scan chain architecture that segments a single scan chain to minimize switching activity during scan shifting is proposed. This approach also greatly reduces average power and can avoid peak power problems during scan shifting, but it will not avoid peak power problems during the ....
Whetsel, L., "Adapting Scan Architectures for Low Power Operation," Proc. of Int. Test Conf., pp. 863-872, 2000.
A Unified Approach to Reduce SOC Test Data Volume, Scan.. - Chandra, Chakrabarty (2003) (Correct)
....the following design techniques. Gated scan chains: These refer to schemes that use gating techniques to clock portions of the scan chain during scan operation [15] 17] In [15] shift registers are used to gate portions of the scan chain during shifting while counters are used for gating in [16]. A decoder multiplexer based architecture for gating scan chains has also been proposed in [17] Modified test pattern generator (TPG) Test generation circuits can be tailored to yield low power vectors without significantly affecting the fault coverage and testing time [18] 19] The method ....
L. Whetsel, "Adapting scan architectures for low power operation," in Proc. Int. Test Conf., 2000, pp. 863--872.
Inserting Test Points to Control Peak Power During Scan.. - Ranganathan.. (Correct)
....99] Dabholkar 98] Girard 99a] Sankaralingam 00, 01] see [Bonhomme 02] for a survey) These techniques are applicable in cases where the heat dissipation during testing exceeds the package s limit. Some design for test (DFT) techniques reduce peak power in addition to average power. In [Whetsel 00] an adapted scan chain architecture that segments a single scan chain to minimize switching activity during scan shifting is proposed. This approach greatly reduces average power and can avoid peak power problems during scan shifting, but requires additional DFT hardware. In [Lee 00] a method ....
Whetsel, L., "Adapting Scan Architectures for Low Power Operation," Proc. of International Test Conference, pp. 863-872, 2000.
Energy-Efficient Logic BIST Based on State Correlation Analysis - Chen, Hsiao (Correct)
....skip, in order to reduce power. In [5] a scheme to partition the scan chain into different groups is presented; together with vector reordering, some scan chains are disabled during testing without damaging fault coverage. Additional control logic and memory are needed for this technique. In [7], the scan chain is also partitioned into groups and only one of them is active for shifting at a time. Test power is thus reduced to approximately 1 N, where N is the number of groups. In [1] the ordinary scan architecture is modified to LT RTPG (low transition random test pattern generator) by ....
L. Whetsel, "Adapting Scan Architectures for Low Power Operation," Proc. of International Test Conference, pp. 863872, 2000
Reducing Power Dissipation During Test Using Scan Chain.. - Sankaralingam, Pouya.. (2001) (Correct)
.... were presented in [Wang 97a] Hertwig 98] Wang 99] Gerstendrfer 99] Girard 99, 00] Techniques for minimizing power dissipation when testing combinational circuits were presented in [Wang 94] Dabholkar 98] and for scan circuits in [Wang 97b] Dabholkar 98] Sankaralingam 00] Whetsel 00] The focus of this paper is on the problem of minimizing power dissipation during scan testing. Wang 97b] modifies the controllability and observability cost functions in PODEM [Goel 81] to find a set of scan vectors that minimizes test power. Sankaralingam 00] describes a guided algorithm ....
....vectors that minimizes test power. Sankaralingam 00] describes a guided algorithm for static compaction of scan vectors to minimize switching activity. Dabholkar 98] proposes heuristic algorithms for test vector ordering and scan chain ordering that minimize average power during scan testing. Whetsel 00] describes an adapted scan chain architecture that segments a single scan chain to minimize switching activity during scan shifting. It should be noted that many methods that are targeted towards reducing test time during scan testing also reduce power dissipation because they result in less ....
Whetsel, L., "Adapting Scan Architectures for Low Power Operation," Proc. Int. Test Conf., pp. 863-872, 2000.
A Novel Scan Architecture for Power-Efficient, Rapid Test - Ozgur Sinanoglu And (2002) (Correct)
No context found.
L. Whetsel, "Adapting Scan Architectures for Low Power Operation ", in ITC, pp. 863--872, 2000.
Test Data Compression: The System Integrator's Perspective - Paul Theo Gonciari (2003) (Correct)
No context found.
L. Whetsel. Adapting Scan Architectures for Low Power Operation. In ITC, pp 863--872, Oct. 2000.
Low-Cost Test For Core-Based System-On-A-Chip - Gonciari (2003) (Correct)
No context found.
L. Whetsel, "Adapting Scan Architectures for Low Power Operation," in Proceedings IEEE International Test Conference (ITC), pp. 863--872, IEEE Computer Society Press, Oct. 2000.
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