Park I., O'Brien K., Jerraya A.A., AMICAL: Architectural Synthesis Based on VHDL", in G. Saucier, J. Trilhe (eds), "Synthesis for Control Dominated Circuits", North-Holland, 1993. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
A Flexible Architecture Representation for High Level Synthesis - Hald, Madsen (1994) (Correct)
....port, which then provokes the module controller to start the execution of the instruction. It is of course also necessary to input operand values and output results from the instruction. The synchronous protocol for these transfers (see fig. 2) is an extended version of the protocol used in AMICAL[3, 4]. The protocol describes the data transfers to take place in a sequence of clock cycles, i.e. it describes how instruction parameters are transferred to ports. Each data transfer description may be augmented with a delay that specifies the setup time for inputs and the output delay for outputs. 4 ....
I. Park, K. O'Brien, A.A. Jerraya. Amical: Architectural synthesis based on vhdl. In G. Saucier, J. Trilhe, editor, Synthesis for Control Dominated Circuits. North-Holland, 1993.
An Approach to Interface Synthesis - Madsen, Hald (21 citations) (Correct)
....determined. This may be reflected in the PFG as illustrated in figure 2b. Each timed event is now associated with an instruction, which must be invoked in order to perform the actual data transfer. The implementation view of the PFG is an extended version of the protocol description used in AMICAL [8]. Example 2: As an example, the PFG of figure 2a, i.e. the specification view, may formally be expressed as: PFGFMULT = a . k b) d : d = 1) c) and the PFG of figure 2b, i.e. the implementation view, as: PFGFMULT = iTRF k a k b) iTEST k d : d = 1) ....
I. Park, K. O'Brien, and A.A. Jerraya. Amical: Architectural synthesis based on vhdl. In G. Saucier and J. Trilhe, editors, Synthesis for Control Dominated Circuits. North-Holland, 1993.
Analysis of Different Protocol Descriptions Styles .. - Pirmez, Pedroza.. (1996) Self-citation (Jerraya) (Correct)
....be defined by adding an outer loop to the process and including an exit outer loop into the corresponding exception clause. This paper discusses the effect of the input description on HLS when using VHDL [22] We will use AMICAL, a VHDL behavioral compiler for control flow dominated machines [12]. In order to show this effect, a high speed protocol based on the ISO reference protocol ABRACADABRA called ABRACADABRA HS was devised. This protocol includes the parameters of most of the existing high performance protocols such as the XTP [2] and the DATAKIT[1] Section 2 presents the ....
....for the treatment of control flow dominated descriptions. It is based on the same principles of path scheduling [19] but significantly reduces the number of the generated paths and hence, the computation cost. DLS has been implemented and integrated with the high level synthesis tool, AMICAL [12]. The main representation used by DLS is a control flow graph (CFG) 20] This kind of representation is well suited to control flow dominated circuits. It provides a convenient means to represent inherent properties of these circuits that are described by nested loops, unstructured control such ....
Park I., O'Brien K., Jerraya A.A., AMICAL: Architectural Synthesis Based on VHDL", in G. Saucier, J. Trilhe (eds), "Synthesis for Control Dominated Circuits", North-Holland, 1993.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC