Jose C. Costa, Paulo F. Flores, Horacio C. Neto, Jose C. Monteiro, and Joao P. Marques Silva. Power Reduction in BIST by Exploiting Don't Cares in Test Patterns. In IEEE/ACM International Workshop on Logic Synthesis (IWLS), pages 375--386, June 1998. Home/Search Document Details and Download
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This paper is cited in the following contexts:
On Reducing the Peak Power Consumption of Test Sequences - Corno Rebaudengo Sonza (1999) (3 citations) (Correct)
.... The approaches dealing with this issue can be classified as: ATPG integrated optimization: the test pattern is optimized for low power during the test generation phase [2] 3] 4] post ATPG optimization: the test pattern is first generated by a classical ATPG, then it is optimized for power [5][6] 7] 8] Power consumption of test sequences for standard sequential circuits were since now addressed by postATPG optimization methods, only. These approaches give good results in term of power consumption reduction, but only when a reduction in the attained fault coverage is allowed. In this ....
J. Costa, P. Flores, H. Neto, J. Monteiro, J. P. Marques Silva, "Power Reduction in BIST by Exploiting Don't Cares in Test Patterns", IEEE IWLS, 1998
Test Pattern Generation under Low Power Constraints - Fulvio Corno Maurizio (Correct)
.... approaches have been proposed, which can be classified as: ATPG integrated optimization: the test pattern is optimized for low power during the test generation phase [4] 5] post ATPG optimization: the test pattern is first generated by a classical ATPG, then it is optimized for power [6][7] 8] 9] The method proposed in this paper stems from the observation that, given a fault to be tested, several sequences may exist able to detect it. The test sequences are equivalent form the point of view of Fault Coverage, but they may show a significantly different behavior as far as the ....
J. Costa, P. Flores, H. Neto, J. Monteiro, J. P. Marques Silva, "Power Reduction in BIST by Exploiting Don't Cares in Test Patterns", IEEE Internation Workshop on Logic Synthesis, 1998
Models and Algorithms for Optimization Problems in Digital.. - Flores (2001) Self-citation (Flores Neto Silva) (Correct)
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Jose C. Costa, Paulo F. Flores, Horacio C. Neto, Jose C. Monteiro, and Joao P. Marques Silva. Power Reduction in BIST by Exploiting Don't Cares in Test Patterns. In IEEE/ACM International Workshop on Logic Synthesis (IWLS), pages 375--386, June 1998.
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