| Vinod Kathail, Michael S. Schlansker, and B. Ramakrishna Rau, "HPL-PD architecture specification: Version 1.1," Tech. Rep. HPL-93-80(R.1), HewlettPackard Company, Feb. 2000. |
.... architecture generated by the Spacewalker (at each search iteration) includes: 1) a specification of the target machine s register files (including width in bits and number of registers, but not number of ports) 2) a specification of the machine s operations, a subset of the HPLPD repertoire [46]; and (3) a characterization of the machine s level of ILP , specified in terms of a number of concurrent and exclusion operation groups constraints note that such constraints are to be later used by the Architecture Synthesis Sub system, to explore opportunities for register port sharing, as ....
Vinod Kathail, Michael S. Schlansker, and B. Ramakrishna Rau, "HPL-PD architecture specification: Version 1.1," Tech. Rep. HPL-93-80(R.1), HewlettPackard Company, Feb. 2000.
....effective optimization on and around predication. These techniques form the foundation of a useful predicated ILP compiler, and were all applied in the experiments that follow. 4. Predication model Most modern implementations of full predication are descended from the HP Labs HPL PD design [14], a generalization of the model developed for the Cydrome Cydra 5 [15] The IMPACT model [16] one derivative, specifies the predicate define: p g ) p d0 t 0 , p d1 t 1 = src 0 cond src 1 ) Here the guard predicate (p g ) and comparison (src 0 cond src 1 , where cond can be = #= etc. ....
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL-PD architecture specification: Version 1.1," Tech. Rep. HPL-93-80 (R.1), HewlettPackard Laboratories, Feb. 2001.
....of the program. In our experiments, all benchmarks in SPEC95int suite run to completion demonstrating that LEGO is a functioning compiler. In this study, the SPEC95int benchmarks are scheduled for an 8 issue VLIW machine model based on the Hewlett Packard Laboratories HPL PD architecture [9,10]. In this machine model, all function units are fully pipelined and all operations have a one cycle latency except for load (two cycles for a hit) floating point add (two cycles) floating point subtract (two cycles) floating point multiply (three cycles) and floating point division (three ....
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL-PD architecture specification: version 1.1." Tech. Rep. HPL-93-80 (R.1), Hewlett--Packard Laboratories, February 2000
.... motion (a) the treegion before the scheduling of candidate op (marked with ) b) the treegion after the scheduling of candidate op In the experimentation, the SPEC95int benchmarks are scheduled for an 8 issue VLIW machine model based on the Hewlett Packard Laboratories HPL PD architecture [7,8]. In this machine model, all function units are fully pipelined and all operations have a one cycle latency except for load (two cycles for a hit) floating point add (two cycles) floating point subtract (two cycles) floating point multiply (three cycles) and floating point ld r1, r2, 5 ( ....
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL-PD architecture specification: version 1.1." Tech. Rep. HPL-93-80 (R.1), Hewlett--Packard Laboratories, February 2000
No context found.
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL-PD architecture specification: version 1.1." Tech. Rep. HPL-93-80 (R.1), Hewlett--Packard Laboratories, February 2000.
No context found.
V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL-PD architecture specification: version 1.1." Tech. Rep. HPL93 -80 (R.1), Hewlett--Packard Laboratories, February 2000.
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