M. Pedram, "Power minimization in IC Design: Principles and applications," ACM Transactions on Design Automaton, vol. 1, no. 1, pp.3-56, Jan. 1996. Home/Search Document Details and Download
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Synthesis of Power-Managed Sequential Components.. - Benini, De.. (Correct)
....The kernel extraction algorithms of Sections VI and VII strive for satisfying all the above requirements. V. RELATED WORK The development of computer aided design techniques for power minimization has been a very active area of research in the last few years (refer to the surveys by Pedram [9] and by Macii et al. 10] for further reading) Our paper is related to a number of sequential power optimization techniques that are briefly summarized next. FSM decomposition for low power [11] 14] can be seen as a top down computational kernel extraction procedure that starts from explicit ....
M. Pedram, "Power minimization in ic design: principles and applications, " ACM Trans. Design Automat. Electron. Syst., vol. 1, no. 1, pp. 3--56, 1996.
FPGA Power Efficient Inverse Lifting Wavelet IP - Grangetto, Martina, Masera.. (Correct)
....low power FPGA can be successfully exploited as an advanced technological layer onto develop new, competitive power conscious solutions. This design flow leads to a good partition between physical and logical contributes for overall system s power consumption estimation. To tackle hazard activity [10], wide use of deeplypipelined units has been employed. In particular, a set of reconfigurable pipelined arithmetic IPs has been developed resorting to VHDL, in order to evaluate different area speed power trade off. Moreover, operand widths can be programmed, introducing new degrees of freedom in ....
M. Pedram, "Power minimization in IC design: principles and applications," ACM Trans. on Design Automation of Electronic Systems, vol. 1, no. 1, pp. 3- 56, January 1996. 1329
Effective Low Power BIST for Datapaths - Gizopoulos Kranitis Paschalis (2000) (3 citations) (Correct)
....Power consumption is a serious consideration in IC design and testing. Low power consumption prolongs the life of the batteries in portable systems, increases the length of the operating periods, and requires less expensive packages and cooling mechanisms, thus decreasing the system cost [1]. Circuit activity that leads to power consumption in CMOS circuits is significantly higher during test or self test intervals [2] Particularly, in BuiltIn Self Test (BIST) a large number of uncorrelated pseudorandom test vectors are applied to the circuit causing a significantly higher circuit ....
M.Pedram, "Power Minimization in IC Design: Principles and Applications", ACM Trans. on Design Automation of Electronic Systems, vol. 1, no.1, pp. 3-56, 1996.
An Analysis of System Level Power Management Algorithms.. - Ramanathan, Irani, Gupta (2002) (Correct)
....computing devices, greater attention has to be paid to power estimation and management techniques. Over the past few years, methods to estimate and minimize power in the design of circuits have been reported. Several excellent reviews of power minimization techniques are presented by Pedram [9], Devadas and Malik [10] Chandrakasan and Brodersen [14] Najm [11] and Luca [26] Low power VLSI design can be achieved at various levels of abstraction during the design process. These include the system level, behavioral level, the RTL level, and the gate level. Most techniques in the ....
M. Pedram. Power Minimization in IC Design: Principles and Applications. ACM Trans. on Design Automation of Electronic Systems, vol 1, no. 1, pages 3-56, January 1996
Determining Optimal Processor Speeds for Periodic - Real-Time Tasks With (Correct)
.... Research Projects Agency through the PARTS (Power Aware RealTime Systems) project under Contract F33615 00 C 1736 Work done while this author was visiting the Information Sciences and Telecommunications Department, University of Pittsburgh For a detailed survey, the reader is referred to [16] and [7] Such on going research has important implications for real time systems design, simply because most of the applications running on power limited systems impose inherently temporal constraints on the response time (such as real time communication and control tasks) Hardware and software ....
M. Pedram. Power Minimization in IC Design: Principles and Applications. ACM Transactions on Design Automation of Electronics Systems. 1:1 - pp. 3-56, January 1996.
System Level Online Power Management Algorithms - Ramanathan, Gupta (2000) (5 citations) (Correct)
.... Level Online Power Management Algorithms Dinesh Ramanathan Rajesh Gupta Center for Embedded Computer Systems Department of Information and Computer Science University of California Irvine, CA 92697 dinesh, rgupta ics. uci. edu Abstract The problem of power management for an embedded system is to reduce system level power dissipation by shutting off parts of the system when they are not being used and turning them back on when they are required. Algorithms for this problem are online ....
....computing devices, greater attention has to be paid to power estimation and management techniques. Over the past few years, methods to estimate and minimize power in the design of circuits have been reported. Several excellent reviews of power minimiza tion techniques are presented by Pedram [6] Devadas and Malik [7] and Najm [8] The authors would like to acknowledge support from National Science Foundation award numbers MIP 95 01615 (CAREER) and CCR 9806898, and from DARPA grant DABT63 98 C 0045. tParts of this work was done while this author was working for CynApps Inc. Santa ....
[Article contains additional citation context not shown here]
M. Pedram. Power Minimization in IC Design: Principles and Applications. ACM Trans. on Design Automation of Electronic Systems, vol 1, no. 1, pages 3-56, January 1996
Low Power Address Encoding using Self-Organizing Lists - Mamidipaka, Hirschberg, Dutt (2001) (7 citations) (Correct)
....the increasing drive towards System On a Chip (SOC) applications, power has become an important parameter that needs to be optimized along with speed and area. Power reduction techniques have been proposed at di erent levels of the design hierarchy from the algorithmic level[3] and system level[11] to the layout level[12] and circuit level[11] The dominant source of power dissipation however, is due to the charging and discharging of node capacitances during transitions, referred to as capacitive power[17, 10] This work was partially supported by grants from NSF (MIP 9708067) DARPA ....
....(SOC) applications, power has become an important parameter that needs to be optimized along with speed and area. Power reduction techniques have been proposed at di erent levels of the design hierarchy from the algorithmic level[3] and system level[11] to the layout level[12] and circuit level[11]. The dominant source of power dissipation however, is due to the charging and discharging of node capacitances during transitions, referred to as capacitive power[17, 10] This work was partially supported by grants from NSF (MIP 9708067) DARPA (F33615 00 C 1632) and Motorola Corporation ....
M. Pedram. Power minimization in IC design: principles and applications. ACM Transactions on Design Automation of Electronic Systems, 1:3-56, 1996.
Dynamic Functional Unit Assignment for Low Power - Steve Haga Natasha (Correct)
....for many computational mod FU FU FU FU FU Alternative routing (57 less energy) Default routing FFF7 0A01 7F00 0111 0A71 0A01 7FFF 0001 FFF7 0A01 7F00 0111 0A71 0A01 7FFF 0001 cycle 2 cycle 1 Figure 1. Alternative data routes for a 3 way processor ules. To begin, it is known [15] that the most important source of power dissipation in a module is the dynamic charging and discharging of its gates, called the switched capacitance. This switched capacitance is dependent upon the module s input values [14] It has been further shown [13, 6] that the Hamming distance of ....
M. Pedram. Power Minimization in IC Design: Principles and Applications. ACM Transactions on Design Automation of Electronic Systems, 1(1):1--54, January 1996.
The Interplay of Power Management and Fault Recovery in.. - Melhem, Mosse, Elnozahy (2003) (1 citation) (Correct)
....the tasks can meet their deadlines and also recover from potential failures. If a failure occurs, we set the processor to operate at maximum speed (and consequently maximum energy consumption) to re execute the lost computation. Power management has recently attracted a large body of research [7, 11, 12, 23, 24, 27, 28, 32, 35 37]. This increasing attention has been motivated initially by the limitations on battery life in portable devices. There are several aspects to the problem, including controlling the power of the processor, display, disk subsystem, and memory [6] The interactions of these techniques with failure ....
M. Pedram. Power minimization in IC design: Principles and applications. ACM Transactions on Design Automation of Electronics Systems, 1(1):3--56, January 1996.
Minimum Energy Fixed-Priority Scheduling for Variable Voltage.. - Quan, Hu (2002) (9 citations) (Correct)
....the system capability accordingly, by shutting down or dynamically varying the processor supply voltage, has been a major strategy to design low power systems. Over the past several years, many methods and techniques for minimizing power consumption for such systems has been published, e.g. [2, 9, 10]. Yet how to achieve the best energy efficiency for many of these systems remains unknown, and how close these approaches are to the optimal solutions is still a question. Power reduction techniques in general can be classified # This work is supported in part by NSF under grant number MIP9701416 ....
M.Pedram. Power minimization in ic design: principles and applications. ACM Trans. on Design Auto. of Electr. Sys., 1(1):3--56, January 1996.
System-Level Power-Aware Design Techniques in Real-Time Systems - Unsal, Koren (Correct)
....substrate (Si) layer. Reducing the term of interest at the system level, maximum power, will also reduce the maximum temperature. Devicelevel related thermal issues are covered in [17] For detailed information about device level power dissipation basics, we refer the reader to [18] 19] 20] [21]. B. What is System Level Power Aware Design All the techniques for system level dynamic power aware design focus on one or more of the terms in Equation 1. This is the case even for CL : the load capacitance may seem to be highly dependent on the physical design process and not affected by ....
M. Pedram, "Power Minimization in IC Design: Principles and Applications ", ACM Transactions on Design Automation of Electronic Systems, vol 1, no 1, Jan. 1996, pp. 3-56.
Power Minimisation Techniques for Testing Low Power VLSI Circuits - Nicolici (2000) (2 citations) (Correct)
....and efficiency of testable design space exploration. The ever increasing demand for portable computing devices and wireless communication systems requires low power VLSI circuits. Minimising power dissipation during the VLSI design flow increases lifetime and reliability of the circuit [29, 158, 169]. Numerous techniques for low power VLSI circuit design were reported [158] for CMOS technology where the dominant factor of power dissipation is dynamic power dissipation caused by switching activity [29, 169] While these techniques have successfully reduced the circuit power dissipation during ....
....demand for portable computing devices and wireless communication systems requires low power VLSI circuits. Minimising power dissipation during the VLSI design flow increases lifetime and reliability of the circuit [29, 158, 169] Numerous techniques for low power VLSI circuit design were reported [158] for CMOS technology where the dominant factor of power dissipation is dynamic power dissipation caused by switching activity [29, 169] While these techniques have successfully reduced the circuit power dissipation during functional operation, testing of such low power circuits has recently ....
[Article contains additional citation context not shown here]
M. Pedram. Power minimization in IC design: Principles and applications. ACM Transactions on Design Automation of Electronic Systems (TODAES), 1(1):3--56, January 1996.
Automated Phase Assignment for the Synthesis of Low.. - Patra, Narayanan.. (1999) (1 citation) (Correct)
....circuits still meet timing constraints. Key words: domino logic circuits, phase assignment, low power synthesis I Introduction The advent of portable digital devices such as laptop computers and cellular phones has made low power circuit design an increasingly important research area [4, 13, 14, 12, 6, 11]. For example, laptop computers have a limited battery life, and so the circuitry in the computer must be designed to dissipate as little power as possible without sacrificing performance in terms of speed. Further more, simultaneous low power and high performance designs are needed beyond the ....
....the supervertices in an s graph should be processed in descending order of their weights. 4.2. 2 Variable Ordering for BDDs Once we have split the loops in the sequential circuit to form a combinational structure we are ready to use BDDs [1] to compute the signal probability at each circuit node [3, 14]. We can greatly reduce the complexity of BDD computations by maximizing sharing of nodes in the ROBDD. Domino blocks have the following properties that allow us to maximize BDD node sharing: 1) The circuits are highly flattened and a node s average fanout is high, 2) The overall circuit is ....
M. Pedram, "Power minimization in IC design: principles and applications," ACM Transactions on Design Automation of Electronic Systems, 1(1), pp. 3-56, 1996.
Dynamic and Aggressive Scheduling Techniques for.. - Aydin, Melhem.. (2001) (33 citations) (Correct)
....of the static power aware scheduling problem is equivalent to solving an instance of the rewardbased scheduling problem [1, 4] with concave reward functions. 1 Introduction In the last decade, the research community has addressed the low power system design problems with a multidimensional effort [7, 18]. Such on going research has important implications for real time systems design, simply because most of the applications running on power limited systems inherently impose temporal constraints on the response time (such as real time communication in satellites) The variable voltage scheduling ....
M. Pedram. Power Minimization in IC Design: Principles and Applications. ACM Transactions on Design Automation of Electronics Systems. 1:1 - pp. 3-56, January 1996.
Integrated Hardware-Software Co-Synthesis and High-Level.. - Doboli (2001) (Correct)
....that exploits slack times. Dave et al. [4] propose a low power co synthesis method that includes allocation, scheduling and performance estimation. Their method is at the task level so that estimation is limited to average power. Also, authors do not consider any low power specific design issues [12] i.e. temporary shut down of unused resources. This paper presents an integrated approach to hardwaresoftware co synthesis and HLS for design of low power embedded systems. Goal is to find the hardware software implementation of a system, that minimizes overall power consumption while satisfying ....
....times and power consumptions specific to all hardware resources that can implement it. The technique suggested by Gupta et al. [9] can be used for ON characterization and the method by Tiwari et al. [17] can be applied for CN characterization. Any dependency of power consumption on input data [12] [11] is addressed at this level. The execution semantics of our model assumes that each CN is executed not more than once for each traversal of the graph. ONs can be executed multiple times with the restriction that the number of iterations is known. Even though system functionality can be ....
[Article contains additional citation context not shown here]
M. Pedram, "Power Minimization in IC Design: Principles and Applications", ACM Trans. on DAES, Vol.1, No.1, 1996, pp.3-56.
Optimal Low Power XOR Gate Decomposition - Hai Zhou Wong (2000) (Correct)
....increase the packaging and cooling costs and shorten the life of ICs. Therefore, low power techniques are also needed. In current technology, power dissipation in digital CMOS circuits is dominated by the dynamic dissipation, which is mainly the charging and discharging of the load capacitances [4]. In a circuit consisting of n gates, it can be modeled as P =0:5V dd f clk C L E sw where Vdd is the supply voltage, f clk is the clock frequency, C L is the load capacitance at the output of gate i, and E sw (referred to as switching activity) is the expected number of gate i ....
M. Pedram. Power minimization in IC design: Principles and application. ACM TODAES, January 1996.
Power Management Points In Power-Aware Real-Time Systems - Melhem, AbouGhazaleh.. (2002) (1 citation) (Correct)
....Advanced Research Projects Agency under contract F33615 00 C 1736 127 efficient way to guarantee the functionality in the upcoming pervasive computing era. The Engineering and Computer Science communities at large confronted the low power system design problems with a multi dimensional effort [12, 28]. Hardware and software manufacturers have agreed to introduce standards such as the ACPI (Advanced Configuration and Power Interface) 16] for power management of laptop computers that allows several modes of operation, such as predictive system shutdown [34] Such on going low power research ....
M. Pedram. Power Minimization in IC Design: Principles and Applications. ACM Transactions on Design Automation of Electronics Systems. 1:1 - pp. 3-56, January 1996.
An Application of Genetic Programming to Electronic.. - Rossi, Liberali.. (2001) (Correct)
....P due to the logic transitions of circuit nodes also increases. It can be expressed as: P = 1 CV f# (1) where C is the total capacitance, V is the power supply voltage, f is the clock frequency, and # is the transition activity, i.e. the average number of logic transitions in a clock period [8, 9]; 3. product testability. The increasing complexity of integrated systems leads to a huge number of internal nodes which cannot be directly controlled and or observed. Since manufacturability requires to test every chip to determine whether it is good or bad, it is apparent that more powerful ....
Pedram, M.: Power minimization in IC design: Principles and applications. ACM Trans. on Design Automation of Electronic Systems 1 (1996) 3--56
Datapath Scheduling using Dynamic Frequency Clocking - Saraju Mohanty Ranganathan (2002) (Correct)
....High level synthesis is the transformation from a behavioral specification of a system to its RTL structure specification [1] The essential tasks involved in synthesis are scheduling, allocation, binding and clock selection. The need for low power synthesis is driven by several factors such as [6]: 1) demand of portable systems (battery life) 2) thermal considerations (cooling and packaging) 3) environmental concerns (natural resources) and (4) reliability issues. The average power dissipation is a concern for the first three factors, whereas, peak power is the critical design ....
....peak power is the critical design concern for reliability. During synthesis, to increase battery life, power delay product has to be minimized, whereas, to increase battery life alongwith delay reduction, energydelay product should be minimized. The three equations for a CMOS circuit are [6, 8] as follows. Energy dissipation per operation, 10 (1) where, is the effective switched capacitance and is the supply voltage. 4,5.6. depends not only on the circuit structure but also on the input pattern applied to the system. With frequency , the power dissipation ....
M. Pedram, "Power Minimization in IC Design : Principle and Applications", ACM Trans. on Design Automation of Electronic Systems, Vol.1, No.1, Jan 1996, pp. 3-56.
Unknown - Los Angeles Ca Self-citation (Pedram) (Correct)
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M. Pedram, "Power minimization in IC Design: Principles and applications," ACM Transactions on Design Automaton, vol. 1, no. 1, pp.3-56, Jan. 1996.
Power Simulation and Estimation in VLSI Circuits - Pedram (1999) (2 citations) Self-citation (Pedram) (Correct)
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M. Pedram, "Power Minimization in IC Design: Principles and Applications," ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 1, pp. 3-56, 1996.
Power-optimal Encoding for DRAM Address Bus - Wei-Chung Cheng And (2000) (4 citations) Self-citation (Pedram) (Correct)
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M. Pedram, "Power minimization in IC design: principles and applications," ACM Trans. on Design Automation of Electronic Systems, Vol. 1, No. 1 (1996), pages 3-56.
Information Theoretic Measures for Power Analysis - Diana Marculescu Radu (1996) (31 citations) Self-citation (Pedram) (Correct)
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M. Pedram, `Power Minimization in IC Design: Principles and Applications', in ACM Transactions on Design Automation of Electronic Systems, vol.1, no.1, pp.1-54, Jan.1996
A Leakage-aware Low Power Technology Mapping - Algorithm Considering The Self-citation (Pedram) (Correct)
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Pedram, M., "Power minimization in IC design: principles and applications," ACM Transactions on Design Automation of Electronics Systems, vol. 1, no. 1, pp. 3-56, 1996.
Massoud Pedram and Qing Wu - Department Of Electrical Self-citation (Pedram) (Correct)
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M. Pedram, "Power Minimization in IC Design: Principles and Applications", ACM transactions on Design Automation of Electronic Systems, Vol. 1, No. 1, pp. 3-56, Jan., 1996.
This project was sponsored in part by NNSF of China.. - Low Power Dcvslcircuits Self-citation (Pedram) (Correct)
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M. Pedram, "Power minimization in IC design: principles and applications," ACM Transactions on Design Automaton of Electronic Systems, 1(1): 3-56, January 1996.
Advanced Power Estimation Techniques - Pedram (1997) (3 citations) Self-citation (Pedram) (Correct)
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M. Pedram. "Power minimization in IC design: principles and applications, " ACM Trans. on Design Automation of Electronic Systems, 1(1): 3-56, January 1996.
High-Level Power Modeling, Estimation, and Optimization - Macii, Pedram, Somenzi (1997) (22 citations) Self-citation (Pedram) (Correct)
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M. Pedram, "Power Minimization in IC Design: Principles and Applications," ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 1, pp. 3-56, 1996.
Technology Mapping for Low Leakage Power and High.. - Effect Consideration .. Self-citation (Pedram) (Correct)
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Pedram, M., "Power minimization in IC design: principles and applications," ACM Transactions on Design Automation of Electronics Systems, vol. 1, no. 1, pp. 3-56, 1996.
A New Design for Double Edge Triggered Flip-flops* - Massoud Pedram Qing Self-citation (Pedram) (Correct)
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M. Pedram, "Power minimization in IC Design: Principles and applications," ACM Transactions on Design Automation of Electronic Systems, vol. 1, pp.3-56, Jan. 1996.
Title Sequence compaction for power estimation: theory and .. - Authors Radu Marculescu Self-citation (Pedram) (Correct)
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M. Pedram, `Power Minimization in IC Design: Principles and Applications', in ACM Transactions on Design Automation of Electronic Systems, vol.1, no.1, pp.1-54, Jan.1996.
Interconnection Analysis for Standard Cell Layouts - Massoud Pedram Bryan Self-citation (Pedram) (Correct)
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M. Pedram. Power minimization in IC design: principles and applications. ACM Trans. on Design Automation of Electronic Systems, 1(1):1--54, January 1996.
Analysis of Power-Clocked CMOS with Application to the - Design Of Energy-Recovery Self-citation (Pedram) (Correct)
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M. Pedram, "Power minimization in IC Design: Principles and applications," ACM Transactions on Design Automaton, Vol.1, No.1, pp.3-56, 1996.
High-Level Power Modeling, Estimation, and Optimization - Macii, Pedram, Somenzi (1997) (22 citations) Self-citation (Pedram) (Correct)
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M. Pedram, "Power Minimization in IC Design: Principles and Applications," ACM Trans. on Design Automation of Electronic Systems, Vol. 1, No. 1, pp. 3-56, 1996.
Propagation Algorithm Of Behavior Probability In - Power Estimation Based Self-citation (Pedram) (Correct)
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M. Pedram, "Power minimization in IC Design: Principles and applications," ACM Trans. on Design Automation of Electronic Systems, vol.1, no. 1, pp.3-56, Jan. 1996.
A New Description of MOS Circuits at Switch-Level - With Applications Massoud Self-citation (Pedram) (Correct)
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M. Pedram, "Power minimization in IC Design: Principles and applications," ACM Transactions on Design Automation of Electronic Systems, vol. 1, no.1, pp.3-56, Jan. 1996.
Supported by the NSF of China (69773034) and DARPA under .. - Synchronous Derived.. Self-citation (Pedram) (Correct)
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M. Pedram, Power minimization in IC Design: Principles and applications, ACM Trans. on Design Automaton, 1(1996)1, 3-56.
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M. Pedram, `Power Minimization in IC Design: Principles and Applications', in ACM Transactions on Design Automation of Electronic Systems, vol.1, no.1, pp.1-54, Jan. 1996.
Theoretical Bounds for Switching Activity Analysis in .. - Marculescu.. (1998) (2 citations) Self-citation (Pedram) (Correct)
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M. Pedram, `Power Minimization in IC Design: Principles and Applications, ' in ACM Trans. on Design Automation of Electronic Systems, vol.1, no.1, pp.1-54, Jan.1996.
Unknown - (Correct)
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M. Pedram, `Power Minimization in IC Design: Principles and Applications,' in ACM Trans. on Design Automation of Electronic Systems, vol.1, no.1, pp.1-54, Jan.1996.
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M. Pedram. Power Minimization in IC Design: Principles and Appications. In ACM Transactions on Design Automation of Electronics Systems, volume 1:1, pages 3--56, January 1996.
On-chip Stack Based Memory Organization for Low Power.. - Mamidipaka, Dutt (2003) (Correct)
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M. Pedram. Power minimization in IC design: principles and applications. ACM TODAES, 1:3--56, 1996.
Dynamic Functional Unit Assignment for Low Power - Haga, Reeves, Barua, Marculescu (Correct)
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M. Pedram. Power Minimization in IC Design: Principles and Applications. ACM Transactions on Design Automation of Electronic Systems, 1(1):1--54, January 1996.
Fir Filter Design Using Low Power Arithmetic Operators - Costa, Bampi, Monteiro (Correct)
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Massoud Pedram. Power Minimization in IC Design: Principles and Applications. ACM Transactions on Design Automation of Electronic Systems, 1(1):3--56, January 1996.
Reducing Switching Activity on Datapath Buses with.. - Kapadia, Benini, De.. (1999) (2 citations) (Correct)
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M. Pedram, "Power minimization in IC design: Principles and applications, " ACM Trans. Design Automat. Electron. Syst., vol. 1, no. 1, pp. 3--56, 1996.
Energy and Transient Power Minimization during Behavioral Synthesis - Mohanty (2003) (Correct)
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M. Pedram, "Power Minimization in IC Design: Principles and Applications," ACM Transactions on Design Automation of Electronic Systems, vol. 1, no. 1, pp. 3--56, Jan. 1996.
On-chip Stack Based Memory Organization for Low Power.. - Mamidipaka, Dutt (2003) (Correct)
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M. Pedram. Power minimization in IC design: principles and applications. ACM TODAES, 1:3--56, 1996.
Energy Efficient Source Code Transformation based on Value.. - Eui-Young Chung Luca (2000) (2 citations) (Correct)
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M. Pedram, "Power minimization in IC design: principles and applications", ACM TODAES, vol. 1, issue 1, pp.3-56, Jan. 1996
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M. Pedram, "Power minimization in IC design: principles and applications," ACM Transactions on Design Automation of Electronic Systems, vol. 1, pp. 3 -- 56, Jan. 1996.
Code Coverage-Based Power Estimation Techniques For Microprocessors - Qu (2002) (Correct)
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M. Pedram, "Power minimization in IC design: principles and applications", ACM Trans. Design Automation of Electronic Syst. 1, 1 (1996) 3--56.
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