S. Ramprasad, N. Shanbhag, I. Hajj, " A Coding Framework for Low Power Address and Data Busses", IEEE Transactions on Very Large Scale Integration Systems, 7:212:221, 1999. Home/Search Document Details and Download
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Low Power Address Encoding using Self-Organizing Lists - Mamidipaka, Hirschberg, Dutt (2001) (7 citations) (Correct)
....the bus width, the data is inverted and put on the bus. An extra bit line is used to signal the inversion on the bus. Variants of T0, T0 BI, Dual T0, and Dual T0 BI[15] are proposed which combine T0 coding with Bus Invert coding. Ramprasad et al. described a generic encoder decoder architecture [13], which can be customized to obtain an entire class of coding schemes for reducing transitions. The same authors proposed INC XOR coding, which reduces the transitions on the instruction address bus better than any other existing technique. An adaptive encoding method is also proposed by Ramprasad ....
....can be customized to obtain an entire class of coding schemes for reducing transitions. The same authors proposed INC XOR coding, which reduces the transitions on the instruction address bus better than any other existing technique. An adaptive encoding method is also proposed by Ramprasad et al.[13] , but with huge hardware overhead. This scheme uses a RAM to keep track of the input data probabilities, which are used to code the data. Another adaptive encoding scheme is proposed by Benini et al. which does encoding based on the analysis of previous N data samples[1] This again has huge ....
[Article contains additional citation context not shown here]
S. Ramprasad, N. R. Shanbag, and I. N. Hajj. A coding framework for low power address and data busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7:212-221, 1999.
An Adaptive Dictionary Encoding Scheme for SOC Data Buses - Lv, Henkel, Lekatsas, Wolf (2002) (Correct)
....In Section 5, we compare our ADES scheme with three other encoding schemes ( Bus Invert , World rig Zone Encoding and Transition Pattern Coding) Finally, Section 6 gives conclusions. 2 Related work Early work on reducing bus power concentrated on reducing the bit transitions (Stan Burleson [1]) The basic idea is to transfer an inverted word through the bus whenever it reduces the Hamming Distance between two successive bus transactions. An additional bus line is used to indicate whether the word is inverted or not. Later in [3] they generalize the Bus Invert Encoding to a spacetime ....
....to system buses. Henkel Lekatsas [6] have proposed an encoding scheme for address buses by first changing the order of bus lines and then applying local bus invert. Macchiarulo et al. 15] have shown that the layout of an address bus can be arranged for low power consumption. Ramprasad et al. [1]) introduced a general communication model to describe low power bus encoding systems. Their bus encoding scheme consists of a source encoding part and a channel encoding part. The exploitation of source properties has been studied in [4] by Musoll et al. who proposed Vorking Zone Encoding (WZE) ....
S. Ramprasad, N. R. Shanbhag, Ibrahim N. Hajj, "A Coding Framework for Low-Power Address and Data Busses", IEEE Tr. on VLSI Systems, Vol. 7, No. 2, pp. 212-221, Jun 1999.
Power Optimization of System-Level Address Buses.. - Fornaciari.. (2000) (8 citations) (Correct)
....savings can be achieved through the reduction of the transition activity of the system buses. The power consumption due to the transition activity of the I O pads in a VLSI circuit ranges from 10 to 80 of the overall power with a typical value of 50 for circuits optimized for low power [1]. Several encoding techniques have been recently proposed in literature to reduce the switching activity of high capacitance bus lines. In [2] the authors have proposed a redundant encoding scheme, the ########## code, which is suitable to transmit patterns randomly distributed in time, such as ....
....on the bus, while the #### addressing requires one bit switching per each pair of consecutive patterns. Other encoding techniques at the system level have been reviewed in [3] while a general encoding decoding framework aiming at reducing the transition activity has been recently proposed in [1]. Although most of the known low power encoding techniques can be implemented by using this framework, the critical path to transmit the information on the bus can have a signi cant impact on the system level performance. Other approaches consist of directly changing the way the information is ....
[Article contains additional citation context not shown here]
S. Ramprasad, N. R. Shanbhag, I. N. Hajj, \A Coding Framework for Low-Power Address and Data Busses," #### ###### ## #### ##### ##### ########### ###### #######,Vol. 7, No. 2, June 1999, pp. 212-221.
Modeling and Minimization of Interconnect Energy Dissipation .. - Taylor, Dey, Zhao (2001) (3 citations) (Correct)
....we propose a method which, in addition to the number of transitions, takes into account the type of transitions which occur. Moreover, recent methods that have been proposed to reduce energy dissipation in on chip interconnects focus on minimizing the number of transitions on the interconnects [5, 6]. However, for interconnects in nanometer technologies, techniques need to be developed which take into account DSM effects, not just the number This work is supported by SRC under contract #98 TJ 648, and NSF under grant #CCR 9912414 Permission to make digital or hard copies of all or part of ....
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A Coding Framework For Low-Power Address and Data Busses", IEEE Trans. on VLSI Systems, 1998.
Coupling-Driven Bus Design for Low-Power Application-Specific.. - Shin, Sakurai (2001) (2 citations) (Correct)
....component to interconnect subsystems for data transfer, should be designed and optimized to consume reasonable power while providing sufficient performance. Although there has been significant work devoted to reduce power consumption of offchip buses with coding techniques [2] 3] 4] 5] [6], 7] the overhead of coding logic in terms of delay, area, and power canPermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies ....
S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A coding framework for low-power address and data busses," IEEE Trans. on VLSI Systems, vol. 7, pp. 212--221, June 1999.
FV Encoding for Low-Power Data I/O - Yang, Gupta (2001) (Correct)
....at these I O pins is even greater than that dissipated at internal capacitances. Therefore techniques for minimizing switching at external address and data buses, even at the expense of a slight increase in switching at internal capacitances, are being investigated for reducing power consumption [1, 2, 3, 4, 5, 6, 7, 8, 9] Many of the encoding schemes, such as the bus invert coding [4] are general and can be applied to both address and data buses. General techniques can only provide modest reductions in switching activity. This is because the characteristics of values sent over data and address buses vary and ....
....the FV encoding scheme with 32 changing ( xed) values reduces switching by 42.7 (29.06 ) Thus, the changing ( xed) value FV encoding scheme outperforms the bus invert coding method by nearly a factor of 4 (2) Comparison with other data bus techniques. Some of the work in this category [5, 6] starts from statistical properties of the data streams and compute codes such that value pairs with higher probablity of occurrence lead to fewer switching transitions. In [5] the authors introduce a generic encoder decoder architecture model and provide a few sample solutions in each module of ....
[Article contains additional citation context not shown here]
S. Ramprasad, N. R. Shanbhag, I. N. Hajj, \A Coding Framework For Low-Power Address and Data Busses,\ IEEE Transactions on VLSI Systems, Vol. 7, No. 2, pages 212-221, June 1999.
A Low-Energy Adaptive Bus Coding Scheme - Bishop, Bahuman (2001) (Correct)
....value is sent instead. Otherwise, the extra line is not asserted and the value is sent as usual. It is noted that transition activity does not necessarily indicate energy consumption in [5] The authors also propose a coding scheme that is tuned to reduce energy lost to interwire capacitance. In [6], a coding scheme is proposed that uses decorrelation and entropy coding. In addition, the authors also examine an adaptive coding scheme. However, the adaptive scheme is not well described and the authors report mixed results for the data examined. 2. Our Work We began our work by extracting ....
S. Ramprasad, N. Shanbhag, I. Hajj, "A Coding Framework for Low-Power Address and Data Busses", IEEE Transactions on VLSI Systems, vol. 7, no. 2, pp. 212-221, June 1999.
Low Power Address Encoding using Self-Organizing Lists - Mamidipaka, Hirschberg (2001) (7 citations) (Correct)
....the bus width, the data is inverted and put on the bus. An extra bit line is used to signal the inversion on the bus. Variants of T0, T0 BI, Dual T0, and Dual T0 BI[15] are proposed which combine T0 coding with Bus Invert coding. Ramprasad et al. described a generic encoder decoder architecture [13], which can be customized to obtain an entire class of coding schemes for reducing transitions. The same authors proposed INC XOR coding, which reduces the transitions on the instruction address bus better than any other existing technique. An adaptive encoding method is also proposed by Ramprasad ....
....can be customized to obtain an entire class of coding schemes for reducing transitions. The same authors proposed INC XOR coding, which reduces the transitions on the instruction address bus better than any other existing technique. An adaptive encoding method is also proposed by Ramprasad et al.[13] , but with huge hardware overhead. This scheme uses a RAM to keep track of the input data probabilities, which are used to code the data. Another adaptive encoding scheme is proposed by Benini et al. which does encoding based on the analysis of previous N data samples[1] This again has huge ....
[Article contains additional citation context not shown here]
S. Ramprasad, N. R. Shanbag, and I. N. Hajj. A coding framework for low power address and data busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7:212--221, 1999.
Reducing Transitions on Memory Buses Using Sectorbased - Encoding Technique Yazdan (Correct)
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S. Ramprasad, N. Shanbhag, I. Hajj, " A Coding Framework for Low Power Address and Data Busses", IEEE Transactions on Very Large Scale Integration Systems, 7:212:221, 1999.
This research was supported in part by DARPA PAC/C.. - Chromatic Encoding Low (Correct)
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S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A coding framework for low-power address and data busses," IEEE Trans. VLSI Systems, vol. 7, no. 2, pp. 212-221, 1999.
ALBORZ: Address Level Bus Power Optimization - Yazdan Aghaghiri Yazdan (Correct)
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S. Ramprasad, N. Shanbhag, I. N. Hajj, " A Coding Framework for Low-Power Address and Data Busses", IEEE transactions on Very Large Scale Integration Systems, Vol 7, No. 2, June 1999
Chromatic Encoding: a Low Power Encoding Technique for - Digital Visual Interface (Correct)
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S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A coding framework for low-power address and data busses," IEEE Transaction on VLSI Systems, Vol. 7, No. 2, pp. 212-221, June 1999.
Memory Bus Encoding for Low Power: A Tutorial - Wei-Chung Cheng And (Correct)
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S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A coding framework for low-power address and data busses," IEEE Trans. on VLSI, Vol. 7, No. 2, pp. 212-221, June 1999.
Transition Reduction in Memory Buses Using - Sector-Based Encoding Techniques (Correct)
No context found.
S. Ramprasad, N. Shanbhag, I. Hajj, "A Coding Framework for Low Power Address and Data Busses," IEEE Transactions on Very Large Scale Integration Systems, Vol. 7, No. 2, pp. 212-221, Jun. 1999.
Bus Energy Reduction by Transition Pattern Coding Using.. - Sotiriadis, Chandrakasan (2003) (Correct)
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S. Ramprasad, N. Shanbhag, and I. Hajj, "A coding framework for lowpower address and data busses," IEEE Trans. VLSI Syst., vol. 7, pp. 212--221, June 1999.
A Bus Energy Model for Deep Submicron Technology - Sotiriadis, Chandrakasan (2002) (3 citations) (Correct)
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S. Ramprasad, N. Shanbhag, and I. Hajj, "A coding framework for lowpower address and data busses," IEEE Trans. VLSI Syst., vol. 7, pp. 212--221, June 1999.
Low-Power Data Memory Communication for Application-Specific .. - Petrov, Orailoglu (2002) (Correct)
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S. Ramprasad and N. R. Shanbhag, "A coding framework for low-power address and data busses", IEEE TVLSI, vol. 7, pp. 212--221, June 1999.
Efficient Power Reduction Techniques for Time.. - Mamidipaka, Dutt.. (2002) (Correct)
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S. Ramprasad, et al. A coding framework for low power address and data busses. IEEE Trans. on VLSI Systems, 7:212--221, 1999.
Power Efficiency through Application-Specific Instruction.. - Petrov, Orailoglu (2003) (Correct)
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S. Ramprasad and N. R. Shanbhag, "A coding framework for low-power address and data busses", IEEE TVLSI, vol. 7, n. 2, pp. 212--221, June 1999.
Power Efficiency through Application-Specific Instruction.. - Petrov, Orailoglu (2003) (Correct)
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S. Ramprasad and N. R. Shanbhag, "A coding framework for low-power address and data busses", IEEE TVLSI, vol. 7, n. 2, pp. 212--221, June 1999.
Chromatic Encoding: a Low Power Encoding Technique for Digital .. - Cheng, Pedram (2003) (Correct)
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S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A coding framework for low-power address and data busses," IEEE Trans. VLSI Systems, vol. 7, no. 2, pp. 212-221, 1999.
Transition Pattern Coding: An approach to reduce.. - Sotiriadis, Wang.. (2000) (Correct)
No context found.
S. Ramprasad, N. Shanbhag, I. Hajj, "A coding framework for low-power address and data busses," IEEE Transactions on VLSI Systems, pp. 212-221, Vol. 7, No. 2, June 1999.
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