A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In Proc. IEEE Design, Automation and Test in Europe Conf. (DATE), 2001.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... power related optimizations for processor design can be broadly classified into two categories (1) work that uses voltage and frequency scaling of the processor core to lower power [13, 21] 2) work that uses gating the ability to turn on and off portions of the core for power management [8, 18, 14, 19, 12, 15, 11]. Our hetero geneous multi core architecture does not preclude the use of these techniques and can potentially address the drawbacks of these techniques to provide much greater power savings. For example, voltage and frequency scaling reduces the parameters of the entire core. While this reduces ....

....even at a lower power setting with voltage and frequency scaling. Furthermore, voltage and frequency scaling is fundamentally limited by the process technology in which the processor is built. Heterogeneous multi core designs address both these deficiencies. Gating based power optimizations [8, 18, 14, 19, 12, 15, 11] provide the option to turn off (gate) portions of the processor core that are not useful to a workload. For example, half of the banks in the branch predictor could be turned off in the example above. However, this kind of gating does not address the power consumption in driving wires across the ....

A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In Proceedings of IEEE Design, Automation and Test in Europe Confeence(DATE), 2001.

....typically at the expense of performance (e.g. 1, 2, 4, 8, 17, 19] Examples of such LPTs are cache reconfiguration and issue width changes. By activating these LPTs dynamically, processors can be more effective. Some of the more advanced proposals for adaptive processors combine several LPTs [7, 12, 13, 15, 21]. # This work was supported in part by the National Science Foundation under grants EIA 0081307, EIA 0072102, and CHE 0121357; by DARPA under grant F30602 01 C 0078; and by gifts from IBM and Intel. Unfortunately, controlling processor adaptation effectively is challenging. Indeed, an adaptive ....

....to adapt the hardware and what specific LPTs to activate. These decisions are usually based on testing a few different configurations of the LPTs and identifying which ones are best, and when. Nearly all existing proposals for adaptive systems follow what we call a Temporal approach to adaptation [1, 2, 4, 6, 7, 8, 9, 12, 15, 19, 21]. In this case, both the testing (or exploration) for the best configuration and the application of the chosen configuration are tied to successive intervals in time. Specifically, to identify the best configuration, the available configurations are typically tested back to back one after another. ....

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A. Iyer and D. Marculescu. Power Aware Microarchitecture Resource Scaling. In Design, Automation and Test in Europe, pages 190--196, March 2001.

....these reasons, we believe that on chip multiprocessors will be used very widely in the future. The remainder of this paper discusses our approach in detail. We are aware of previous research that used runtime adaptability for scaling on chip memory cache sizes (e.g. 1] and issue widths (e.g. [6]) among other processor resources. However, to the best of our knowledge, this is the first study that employs runtime resource adaptability for on chip multiprocessors. Recently, there have been several efforts for obtaining accurate energy behavior for on chip multiprocessing and communication ....

A. Iyer and D. Marculescu. Power-Aware Microarchitecture Resource Scaling. In Proceedings of IEEE Design, Automation, and Test in Europe Conference, Munich, Germany, March 2001.

....increased energy consumption in the small cache configuration, is able to get al..most 5 energy savings with only a 1 slowdown. 6. 3 Dynamic Processor Width Adaptation One way to reduce the energy consumption in a processor is to reduce the number of instructions entering the pipeline every cycle [12, 1]. We call this adjusting the width of the processor. Reducing the width of the processor reduces the demand on the fetch, decode, functional units, and issue logic. Certain phases can have a high degree of instruction level parallelism, whereas other phases have a very low degree. Take for example ....

....processor for phases that have low IPC, while still using aggressive widths for phases with high IPC. In the current literature, decisions to reduce or increase the fetch decode issue bandwidth of the processor are made either at fixed intervals (relatively short intervals such as 1,000 cycles) [12] or, as in the case of branch confidence based schemes, when a branch instruction is fetched [1] It can very difficult to design real systems that save energy by reconfiguring at these speeds, but a hardware phase tracker can help make these decisions at a coarser granularity while still ....

A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In Proceedings of the DATE 2001.

....scaling. There has also been a lot of work on system level power anal 2.5 3 3.5 0 0.5 1 1.5 2 1 2 3 4 5 6 7 8 3 Everage Power (W) Switching Frequency (Hz) Vdd (W) Average Power of Bus Line Figure 2: Bus Power Dissipation Pattern ysis for software power dissipation. In [6], profiling hardware is used to identify tightly coupled regions of code and dynamically optimize the configuration of the microprocessor so as to minimize performance penalty. Our work is similar to this approach in the sense that we set the performance parameters, namely, voltage and frequency ....

A. Iyer and D. Marculescu, "Power Aware Microarchitecture Resource Scaling," Proceedings of Design Automation and Test in Europe, pp. 190-196, March 2001.

....digital infrastructure, their cost and short battery life are factors that are holding back their enormous potential. While economic factors will reduce the former, mechanisms are needed to enable executing programs to adapt to dwindling battery life. Many such techniques have been proposed [18, 13, 20, 14, 12, 24] that facilitate energy conservation through di#erent modes of operation at both the device and device component level, i.e. active, idle, standby, and sleep modes [16, 13, 14, 12, 24] Other techniques select instructions based on their energy consumption [15, 22, 23, 20] A key feature of ....

....to enable executing programs to adapt to dwindling battery life. Many such techniques have been proposed [18, 13, 20, 14, 12, 24] that facilitate energy conservation through di#erent modes of operation at both the device and device component level, i.e. active, idle, standby, and sleep modes [16, 13, 14, 12, 24]. Other techniques select instructions based on their energy consumption [15, 22, 23, 20] A key feature of these low level techniques is that they model the power dissipation associated with a particular subsystem within a computational device. Much work [22, 23, 15, 20, 19, 17] has focused on ....

A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In Proc. IEEE Design, Automation and Test in Europe Conf. (DATE), 2001.

....for significant (upward of 20 ) energy savings, over software techniques, which in themselves involve the execution of instructions which consume energy. Hardware architectures which adapt to application needs, by reconfiguring to match applications and save energy have been proposed in [2, 12, 18]. In [12] the authors detail a scheme for adjusting the number of hardware units, in this case resource reservation units in use, in a model of the SimpleScalar architecture, in order to reduce power consumption and overall energy consumption. The authors further propose applying the architecture ....

....(upward of 20 ) energy savings, over software techniques, which in themselves involve the execution of instructions which consume energy. Hardware architectures which adapt to application needs, by reconfiguring to match applications and save energy have been proposed in [2, 12, 18] In [12], the authors detail a scheme for adjusting the number of hardware units, in this case resource reservation units in use, in a model of the SimpleScalar architecture, in order to reduce power consumption and overall energy consumption. The authors further propose applying the architecture to ....

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A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In Proceedings of 2000.

....at least two forms of hardware adaptation. The first is dynamic voltage scaling (DVS) 10, 11, 12, 20, 25, 26, 27, 29] Reducing voltage reduces energy, but also requires reducing frequency, increasing execution time. The second technique adapts the architecture to reduce the effective capacitance [1, 8, 9, 17, 22, 23]. Since a lower effective capacitance often results in a lower IPC and vice versa, a net reduction in energy results only if the ratio of the two terms is reduced. Further, reducing IPC increases execution time. 1 The energy equation assumes dynamic power is dominant, as in current systems. ....

.... parts of the cache [1] Most studies have considered only one of these forms of adaptation (e.g. 1, 8, 9, 10, 11, 20, 22, 23, 25, 26, 27, 29] and most studies of architectural adaptation target general applications without exploiting common characteristics of multimedia applications (e.g. [1, 8, 13, 17, 22, 23]) This paper makes two contributions. First, we develop an integrated algorithm to control both architectural adaptation and DVS for saving processor energy for multimedia applications. The algorithm was partly outlined in our previous work [14] Second, we use the algorithm to understand the ....

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A. Iyer and D. Marculescu. Power Aware Microarchitecture Resource Scaling. In Proc. of the Design, Automation and Test in Europe Conf., 2001.

....[3] presents a compiler driven code layout technique to exploit a specialized cache storing instructions from critical loops. Emerging microarchitecture driven power optimization techniques aim at dynamically reconfiguring the hardware resources, according to the parallelism in the program. In [23, 19] the information on code parallelism and the most efficient hardware configuration adapted to exploit it is either pre computed and stored in code annotations or computed on the fly, using run time profiling techniques. Dynamic voltage scaling under operating system control using interval based ....

A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In DATE, March 2001.

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A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In Proc. IEEE Design, Automation and Test in Europe Conf. (DATE), 2001.

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A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In Design, Automation and Test in Europe, pages 190--196, Munich, Germany, Mar. 2001.

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A. Iyer, D. Marculescu. Power aware microarchitecture resource scaling. In Proc. DATE'01, pages 190--196, Mar. 2001.

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A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In IEEE Design, Automation and Test in Europe Conference, 2001.

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A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In Proceedings of the Design Automation and Testing in Europe, pages 190--196. March 2001.

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A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In Design, Automation and Test in Europe, pages 190--196, Munich, Germany, Mar. 2001.

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A. Iyer and D. Marculescu, "Power aware microarchitecture resource scaling," in Proc. Design Automation & Test Europe (DATE) Conf., pp. 190--196, Mar. 2001.

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A. Iyer and D. Marculescu, "Power aware microarchitecture resource scaling", Proc. IEEE DATE, pp. 190-196, 2001.

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A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling. In IEEE Design, Automation and Test in Europe Conference, 2001.

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