Nickerson, B. R. Graph coloring register allocation for processors with multi-register operands. SIGPLAN Notices 25, 6 (June 1990), 40--52. In Proceedings of the ACM SIGPLAN '90 Conference on Programming Language Design and Implementation.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....by Chow and Hennessy [10, 11] These two techniques have formed the core around which a rich literature has emerged (see Section 7) The techniques used in building graph coloring allocators can be improved. In recent years, several important extensions to Chaitin s basic techniques have appeared [2, 30]. Nevertheless, problems remain. In practice, most of these problems appear as either over spilling or a poor spill choice. In the former case, the allocator fails to keep some value in a register, even though a register is available throughout its lifetime. In the latter case, the allocator ....

Nickerson, B. R. Graph coloring register allocation for processors with multi-register operands. SIGPLAN Notices 25, 6 (June 1990), 40--52. In Proceedings of the ACM SIGPLAN '90 Conference on Programming Language Design and Implementation.

....the combined live range can be done by simply changing lr 3 s parent to point to itself. 4.2.6 Maintaining the simplifiability (colorability) invariant The step that maintains simplifiability ensures that the invariant holds by performing simplification on GR 1 [R 2 . The algorithm described in [52] is used to deal with register pairs. This step consists of four major components as depicted in Figure 4.10: computing degree, removing a LS N node (degree less than N) lowering register pressure, and committing the live range unioning decision. The shaded region simplifies the interference ....

B. R. Nickerson. Graph coloring register allocation for processors with multi-register operands. In Proc. ACM SIGPLAN'90 Conf. on Prog. Language Design and Implementation, pages 40--52. ACM, June 1990.

....the instruction set restricts allocation to only one of the two banks. As we illustrate later, the Intel x86 ISA exhibits both of these kinds of irregularities. The literature on graph coloring register allocation is not entirely devoid of work on irregular architectures. In particular, Nickerson [9] and Briggs [2,3] both describe approaches that adapt graph coloring based allocators for regular architectures to a limited class of irregular architectures. These authors realized that the kinds of irregularities described above directly affect a graph coloring allocator s interpretation of ....

....allocation on irregular architectures is to find an accurate way to determine the colorability of each register candidate in the interference graph. A complete solution to this challenge must address both of the following two characteristics of irregular architectures. First, as Nickerson [9] states, register candidates requiring multiple registers destroy the equivalence between the number of interference relations (edges) in the interference graph and the number of coloring constraints they imply. In other words, a multi register neighbor of a node n implies more than one coloring ....

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B. Nickerson, "Graph Coloring Register Allocation for Processors with Multi-Register Operands," Proc. SIGPLAN'90 Conf. on Programming Language Design and Implementation, pp. 40--52, June 1990.

....and Systems, Vol. XX, No. X, XXXX, 199X. Fusion based register allocation Delta 23 4.2.6 Maintaining the simplifiability (colorability) invariant. The step that maintains simplifiability ensures that the invariant holds by performing simplification on G R 1 [R 2 . The algorithm described in [33] is used to deal with register pairs. This step consists of four major components as depicted in Figure 15: computing degree, removing a LS N node (degree less than N) lowering register pressure, and committing the live range unioning decision. The shaded region is iterated until an empty graph ....

B. R. Nickerson. Graph coloring register allocation for processors with multi-register operands. In Proc. ACM SIGPLAN'90 Conf. on Prog. Language Design and Implementation, pages 40--52. ACM, June 1990.

....the shift instructions on the ROMP microprocessor the engine in RT PC workstations [10] In 1990, Nickerson published a method for allocating structures into an aggregate set of adjacent registers. He observed that an allocator based on our 1989 paper produced good allocations under his scheme [2, 12]. This paper explores the issues that arise when a Chaitin style allocator encounters code that uses both single registers and register pairs. It explores various ways to represent register pairs in the interference graph. It shows why Chaitin s algorithm over estimates demand for registers and ....

....times as much as the single word version fld.l [11] Naturally, any appreciable use of this feature ties down a large number of registers and allocating them carefully becomes very important. Previous work by Nickerson focuses on allocating aggregate data structures to adjacent sets of registers [12]. Nickerson assumes that the data items must remain adjacent throughout their lifetimes and that the components of the aggregate can have different lifetimes. In our work, we handle cases where the components of an aggregate have different lifetimes by enforcing adjacency only at those ....

B. R. Nickerson. Graph coloring register allocation for processors with multi-register operands. In Proceedings of the ACM SIGPLAN '90 Conference on Programming Language Design and Implementation, SIGPLAN Notices, 25(6), pages 40--52, June 1990.

....by Chow and Hennessy [10, 11] These two techniques have formed the core around which a rich literature has emerged (see Section 7) The techniques used in building graph coloring allocators can be improved. In recent years, several important extensions to Chaitin s basic techniques have appeared [2, 28]. Nevertheless, problems remain. In practice, most of these problems appear as either over spilling or a poor spill choice. In the former case, the allocator fails to keep some value in a register, even though a register is available throughout its lifetime. In the latter case, the allocator ....

Nickerson, B. R. Graph coloring register allocation for processors with multi-register operands. SIGPLAN Notices 25, 6 (June 1990), 40--52. In Proceedings of the ACM SIGPLAN '90 Conference on Programming Language Design and Implementation.

....compilers, linkers, must deal with to create optimal register allocations. Dealing with processors that can address multiple registers for an operand does not fit into the typical graph coloring algorithm. Allocation for single and multiple register operands must occur at the same time[15]. Pre allocating instructions that use multiple register operands results in artificially enhancing the priority of the instruction. Allocating multiple register operands after single register operands extends the schedule because of the difficulty in finding the required word and double word ....

....counts the number of basic blocks, block count , within each loop. The loop is unrolled until block count 2 approaches block limit . Basic Block Cloning 68 Cloning is the duplication of basic blocks in a flow graph that have more than one predecessor. This process is similar to tail duplication[15]. Each predecessor branches to a copy of the cloned basic block. An example of a basic block with more than one predecessor is the basic block at the confluence point for an if then else statement. This basic block has two predecessors; one from the then branch, and one from the else branch. ....

Nickerson, B., "Graph Coloring Register Allocation for Processors with MultiRegister Operands", Proceedings of the ACM SIGPLAN `90 Conference on Programming Language Design and Implementation, pp. 40-52, 1990.

....pairs is described in [Bri92] This technique handles the architectural 8 CHAPTER 2. PREVIOUS WORK constraints that often arise when handling multi register values, for example that two registers must be consecutive and evenly aligned. A similar technique was independently developed by Nickerson [Nic90] Priority based colouring An alternative graph colouring method, called priority based colouring, have been presented by Chow and Hennessy [CH84, CH90] Here, instead of using spilling as the main method to reduce the complexity of the interference graph, they use live range splitting. By ....

....often provided that the registers are consecutive and evenly aligned. This could probably pay ooe well in an implementation of a lazy functional language, where complete nodes, i.e. several words, are loaded and stored all the time. We intend to try some technique for this, inspired by Nickerson [Nic90] and Briggs [Bri92] The inode liftingj mentioned above is in some sense very similar to the problem of allocating array elements to registers. In [CCK90] and [DGS92] the allocation of subscripted variables is discussed. Hopefully it will be possible to benet from their results. Appendix A A ....

B.R. Nickerson. Graph coloring register allocation for processors with multi-register operands. In Proceedings of the ACM SIGPLAN '90 Conference on Programming Language Design and Implementation, volume 25, pages 4052, White Plains, NY, June 1990.

....of work building on the foundation provided by Chaitin. We have reported an improvement to Chaitin s coloring heuristic [12] Other improvements were introduced by Bernstein et al. 9] Extensions to enable allocation of register pairs have been discovered by Nickerson and as part of our own work [57, 13]. Recently, we have described a technique for improving the accuracy of spill code estimation and placement [14] An alternative form of global register allocation via graph coloring is described by Chow and Hennessy [22, 25, 26] Their work, while based on coloring, differs in many respects from ....

....on the ROMP microprocessor the engine in RT PC workstations [43] In 1990, Nickerson published a method for allocating structures into an aggregate set of adjacent registers. He observed that an allocator based on our 1989 paper (see Chapter 3) produced good allocations under his scheme [57, 12]. This chapter describes work performed independently of Nickerson and completed at approximately the same time. We consider various ways to represent register pairs in the interference graph. We show why Chaitin s coloring heuristic over estimates demand for registers and how the heuristic ....

[Article contains additional citation context not shown here]

Brian R. Nickerson. Graph coloring register allocation for processors with multi-register operands. SIGPLAN Notices, 25(6):40--52, June 1990. Proceedings of the ACM SIGPLAN '90 Conference on Programming Language Design and Implementation.

....breaking a lifetime into small pieces, and not as eliminating it from the conflict graph. The problem of spilling has lead to two different graph based register allocation algorithms. The original paper by Chaitin [CAC 81] was refined in [Cha82] and more recently by others [BGG 89] BCKT89] and [Nic90]. Meanwhile [CH84] adapted the graph coloring model to use a very different method of spilling. LH86] presents his implementation of a Chow type allocator. This section will examine aspects of the various allocation schemes and describe their implementation in the RTL System. Chapter 14 ....

Brian R. Nickerson. Graph coloring register allocation for processors with multi-register operands. In Proceedings of the SIGPLAN '90 Symposium on Programming Language Design and Implementation, SIGPLAN Notices, pages 40--52, 1990.

....allocators. Briggs et al. discuss modifications to the coloring heuristic to reduce spilling [BCKT89] Bernstein et al. provide new heuristics for selecting candidates to spill [BGG 89] Nickerson presents extensions that enables the allocator to deal with multi register operands [Nic90] A different approach to register allocation via graph coloring, known as priority based coloring, builds a coarser interference graph [CH90] Vertices in this graph represent live ranges, as opposed to Chaitin style allocators where nodes traditionally represent variables or compiler generated ....

Brian R. Nickerson. Graph coloring register allocation for processors with multiregister operands. SIGPLAN Notices, 25(6):40--52, June 1990. Proceedings of the ACM SIGPLAN '90 Conference on Programming Language Design and Implementation.

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B. R. Nickerson, `Graph coloring register allocation for processors with multi-register operands', SIGPLAN Notices, 25, 40--52 (1990).

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