| T. Ananthamaran and R. Bisiani. A hardware accelerator for speech recognition algorithms. In Proceeedings of the 13th International Symposium on Computer Architecture, June 1986. |
....AT T s Graph Search and ASPEN Tree Machines, SRIBerkeley s Speech search machine, and CMU s PLUS architecture. These machines are all custom designed parallel architectures specialized for graph or tree searching, albeit for older technologies and smaller vocabularies. Anantharaman and Bisiani [1] describe two custom pipelined architectures for the beam search in a speech recognition algorithm. Our study of the potential parallelization of SPHINX is orthogonal to these studies, in that we measure the available degree of parallelization in the beam search and possible speedups over ....
T.S. Anantharaman and B. Bisiani. A hardware accelerator for speech recognition algorithms. In Proceedings of the 13th Annual International Symposium on Computer Architecture, pages 216--223, 1986.
....speech a primary human machine interface in the near future. In this context, there is a dearth of information on the performance of speech recognition applications on the common computing platforms of today. Special purpose hardware architectures have been proposed for speech in the late 80 s [2] [7] but these studies are outdated and inadequate in the context of trends of growing vocabularies and the use of general purpose platforms in a multiprogramming environment. In this paper, we examine SPHINX [9] a system for speaker independent, large vocabulary, continuous speech recognition. ....
T.S. Anantharaman and B. Bisiani. A hardware accelerator for speech recognition algorithms. In Proceedings of the 13th Annual International Symposium on Computer Architecture, pages 216-223, 1986.
No context found.
T. Ananthamaran and R. Bisiani. A hardware accelerator for speech recognition algorithms. In Proceeedings of the 13th International Symposium on Computer Architecture, June 1986.
No context found.
T. Ananthamaran and R. Bisiani. A hardware accelerator for speech recognition algorithms. In Proceeedings of the 13th International Symposium on Computer Architecture, June 1986.
No context found.
T. Ananthamaran and R. Bisiani. A hardware accelerator for speech recognition algorithms. In Proceeedings of the 13th International Symposium on Computer Architecture, June 1986.
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