J. He. Formal Specification and Analysis of Digital Hardware Circuits in LOTOS, August 2000. Technical Report CSM-158. University of Stirling. Home/Search Document Details and Download
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Formally-Based Design Evaluation - Turner, He (2001) Self-citation (He) (Correct)
....successfully. Again, the authors had discovered a flaw in a supposedly verified design. 4.3 Asynchronous FIFO As a typical asynchronous circuit, an asynchronous FIFO buffer was specified and analysed. For brevity the specifications and formal analysis are not given here, but can be found in [7, 8, 14]. The FIFO has two inputs InT, InF and two outputs OutT, OutF. Its inputs and outputs use dual rail encoding in which one bit needs two signal lines. A possible implementation for a FIFO stage is given in figure 1 (a) Apart from the data path, there are two lines that control data transmission. ....
....OutT 0 OutF 1 # InF 0 OutF 0 InT 1 OutT 1 InT 0 InT 1 OutT 0 OutT 1 # InT 0 OutT 0 # Pass 4.4 Selector A selector (an asynchronous design component) allows non deterministic choice of output. For brevity the specifications and formal analysis are not given here, but can be found in [7, 8, 14]. After a change on input Ip, either Op1 or Op2 may change depending on the implementation. Figure 3 gives its LTS (minimised with respect to observational equivalence) the suspension automaton of the LTS, and one of the test cases. Sample test T4 shows that after input Ip 1, an implementation ....
Ji He. Formal specification and analysis of digital hardware circuits in LOTOS. Technical Report CSM-158, Department of Computing Science and Mathematics, University of Stirling, UK, Aug. 2000.
Formally-Based Design Evaluation - Turner, He (2001) Self-citation (He) (Correct)
....and its specification. The approach is illustrated with various benchmark circuits as case studies. Keywords: asynchronous design, conformance, LOTOS (Language Of Temporal Ordering Specification) synchronous design, test generation, verification 1 Introduction DILL (Digital Logic in LOTOS [7 13, 19]) is an approach for specifying digital circuits using LOTOS (Language Of Temporal Ordering Specification [6] DILL has been developed over six years to allow formal specification of hardware designs, represented using LOTOS at various levels of abstraction. DILL addresses functional and timing ....
....successfully. Again, the authors had discovered a flaw in a supposedly verified design. 4.3 Asynchronous FIFO As a typical asynchronous circuit, an asynchronous FIFO buffer was specified and analysed. For brevity the specifications and formal analysis are not given here, but can be found in [7, 8, 14]. The FIFO has two inputs InT, InF and two outputs OutT, OutF. Its inputs and outputs use dual rail encoding in which one bit needs two signal lines. A possible implementation for a FIFO stage is given in figure 1 (a) Apart from the data path, there are two lines that control data transmission. ....
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Ji He. Formal Specification and Analysis of Digital Hardware Circuits in LOTOS. PhD thesis, Department of Computing Science and Mathematics, University of Stirling, UK, Apr. 2000.
Formal Verification of Distributed Mutual-Exclusion.. - Meolic, Kapus, Dugonik.. (Correct)
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J. He. Formal Specification and Analysis of Digital Hardware Circuits in LOTOS, August 2000. Technical Report CSM-158. University of Stirling.
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