W. J. Dally and A. Chang, "The role of custom design in ASIC chips," in Proc. Design Automation Conf., 2000, pp. 643--647. Home/Search Document Details and Download
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Power Minimisation Techniques for Testing Low Power VLSI Circuits - Nicolici (2000) (2 citations) (Correct)
.... use of hard macro implementations of library modules which have identical physical and structural information can significantly improve the final design [39] Furthermore, design methodologies which use regular elements and identify similarity need to be incorporated in state of the art CAD tools [39, 50]. Therefore the proposed BIST methodology is targeting design flows that use few pre designed module types with identical physical and structural information and exploits the regularity of the data path to reduce test application time and BIST area overhead as explained in the following example. ....
W.J. Dally and A. Chang. The role of custom design in ASIC chips. In Proc. 37th IEEE/ACM Design Automation Conference (DAC), pages 643--647, 2000.
Future Performance Challenges in Nanometer Design - Sylvester, Kaul (2001) (1 citation) (Correct)
....Advances in library generation, and synthesis tools that take advantage of improved libraries, can together yield more automated, less expensive design flows. Recent work claims libraries are one important reason that custom designs are significantly faster (6 8X) than counterpart ASIC designs [14,15]. For instance, 15] asserts that the lowest performance level (smallest) gates in modem libraries are nearly 10X larger than minimum sized gates, leading to major power increases due to overdriving small loads. However, most current libraries contain a large number of drive strengths, including ....
....generation, and synthesis tools that take advantage of improved libraries, can together yield more automated, less expensive design flows. Recent work claims libraries are one important reason that custom designs are significantly faster (6 8X) than counterpart ASIC designs [14,15] For instance, [15] asserts that the lowest performance level (smallest) gates in modem libraries are nearly 10X larger than minimum sized gates, leading to major power increases due to overdriving small loads. However, most current libraries contain a large number of drive strengths, including some very near ....
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W.J. Dally and A. Chang, "The role of custom design in ASIC chips," Proc. DAC, pp. 643-647, 2000.
BIST Hardware Synthesis for RTL Data Paths Based.. - Nicolici.. (2000) (2 citations) (Correct)
.... use of hard macro implementations of library modules which have identical physical and structural information can significantly improve the final design [31] Furthermore design methodologies which use regular elements and identify similarity need to be incorporated in state of the art CAD tools [31, 32]. Therefore the proposed BIST methodology is targeting design flows that use few pre designed module types with identical physical and structural information and exploits the regularity of the data path to reduce test application time and BIST area overhead as explained in the following example. ....
W.J. Dally and A. Chang, "The role of custom design in ASIC chips," in Proc. 37th IEEE/ACM Design Automation Conference, pp. 643--647, 2000.
Optimality and Scalability Study of Existing Placement.. - Chang, Cong, Romesis, Xie (2004) (6 citations) Self-citation (Chang) (Correct)
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W. J. Dally and A. Chang, "The role of custom design in ASIC chips," in Proc. Design Automation Conf., 2000, pp. 643--647.
Optimality and Scalability Study of Existing Placement.. - Chang, Cong, Romesis, Xie (2004) (6 citations) Self-citation (Chang) (Correct)
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W. J. Dally and A. Chang, "The role of custom design in ASIC chips," in Proc. Design Automation Conf., 2000, pp. 643--647.
The VLSI Implementation and Evaluation of Area- and.. - Khailany (2003) (5 citations) Self-citation (Dally) (Correct)
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William J. Dally and Andrew Chang. The role of custom designs in ASIC chips. In Proceedings of 37th Design Automation Conference, pages 643--647, June 2000.
The VLSI Implementation and Evaluation of Area- and.. - Khailany (2003) (5 citations) Self-citation (Dally) (Correct)
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William J. Dally and Andrew Chang. The role of custom designs in ASIC chips. In Proceedings of 37th Design Automation Conference, pages 643--647, June 2000.
A Design Environment for High-Throughput - Low-Power Dedicated Signal (Correct)
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W. J. Dally and A. Chang, "The role of custom design in ASIC Chips," in Proc. Design Automation Conf., June 2000, pp. 643--647.
Spatial Computation - Mihai Budiu Girish (2004) (Correct)
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W. J. Dally and A. Chang. The role of custom design in ASIC chips. In Design Automation Conference (DAC), Los Angeles, CA, June 2000.
Spatial Computation - Budiu, Venkataramani, Chelcea.. (2004) (Correct)
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W. J. Dally and A. Chang. The role of custom design in ASIC chips. In Design Automation Conference (DAC), Los Angeles, CA, June 2000.
Constructive Benchmarking for Placement - David Papa Department (Correct)
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W. J. Dally and A. Chang, "The Role of Custom Design in ASIC Chips", DAC 00, pp. 643-647.
Benchmarking for Large-scale Placement and beyond - Adya, Yildiz, Markov.. (2003) (8 citations) (Correct)
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W. J. Dally and A. Chang, "The Role of Custom Design in ASIC Chips", DAC 2000, pp. 643-647.
On Whitespace and Stability in Mixed-Size Placement and.. - Adya, Markov.. (2003) (Correct)
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W. J. Dally and A. Chang, "The Role of Custom Design in ASIC Chips", DAC 2000, p. 643-647.
On Whitespace and Stability in Mixed-Size Placement and.. - Adya, Markov.. (2003) (Correct)
No context found.
W. J. Dally and A. Chang, "The Role of Custom Design in ASIC Chips", DAC 2000, p. 643-647.
Benchmarking For Large-scale Placement and Beyond - Saurabh Adya Mehmet (2003) (5 citations) (Correct)
No context found.
W. J. Dally and A. Chang, "The Role of Custom Design in ASIC Chips", DAC 00, p. 643-647.
Benchmarking For Large-scale Placement and Beyond - Saurabh Adya Mehmet (2003) (5 citations) (Correct)
No context found.
W. J. Dally and A. Chang, "The Role of Custom Design in ASIC Chips", DAC 00, p. 643-647.
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