Escalante, M. A., Probabilistic Timing Verification and Timing Analysis for Synthesis of Digital Interface Controllers, Ph.D Dissertation, Dept. of Electrical and Computer Engineering, University of Victoria, 1998.  Home/Search   Document Details and Download   Summary   Related Articles

....as a timing constraint. Each timing constraint is verified at the maximum and minimum values of the interface parameters. The approach taken for the analysis of the timing constraints was conservative. An approach based on probabilistic evaluation of timing constraints as proposed by Escalante [26] may provide a more accurate estimation of the actual behavior and performance of the interface. The primary goal of this work is to produce real world designs: an automated system that actually generates a data transfer interface between components. In producing such a design it was found that a ....

Escalante, M. A., Probabilistic Timing Verification and Timing Analysis for Synthesis of Digital Interface Controllers, Ph.D Dissertation, Dept. of Electrical and Computer Engineering, University of Victoria, 1998.

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