W.-C. Park, S.-W. Lee, O.-Y. Kown, T.-D. Han, and S.-D. Kim. Floating point adder/subtractor performing ieee rounding and addition/subtraction in parallel. IEICE Transactions on Information and Systems, E79-D(4):297--305, Apr. 1996. Home/Search Document Details and Download
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This paper is cited in the following contexts:
Reduced Latency IEEE Floating-Point Standard Adder.. - Beaumont-Smith.. (Correct)
....based on the sequence of significand operations: swap, shift, add, normalise and round. They also discuss how to construct faster FP adders. Implementations of FP adders are reported in [6, 7, 12, 5, 9, 13, 10] Algorithms and circuits which have been used to improve their design are described in [17, 8, 3, 20, 16, 21, 15, 22, 19]. Some of these improvements are as follows: ffl the serial computations such as additions can be reduced by placing extra adders (or parts thereof) in parallel to compute speculative results for exponent subtraction (E a Gamma E b and E b Gamma E a ) and rounding (M a M b and M a M b 1) ....
....phases are disjoint operations for large shifts. However there is a significant increase in hardware cost since the significand addition hardware cannot be shared as with the traditional three stage pipeline. Other FP adder designs have moved the rounding stage before the normalisation [21, 19, 12]. Quach and Flynn describe an FP adder [21] which uses a compound significand adder with two outputs plus a row of half adders and effectively has a duplicated carry chain. Kowaleski et al. 12] describe an adder as part of a 263,000 transistor FP unit which contains separate add and multiply ....
W.-C. Park, S.-W. Lee, O.-Y. Kown, T.-D. Han, and S.-D. Kim. Floating point adder/subtractor performing ieee rounding and addition/subtraction in parallel. IEICE Transactions on Information and Systems, E79-D(4):297--305, Apr. 1996.
A Floating Point Multiplier Performing IEEE Rounding and.. - Park, Han, Kim, Yang (1998) (4 citations) Self-citation (Park Han Kim) (Correct)
....operations can be achieved and only reasonable chip area is required in this approach. Since the IEEE standard 754 [13] has been published, almost all the FPUs follow the IEEE standard 754. Rounding operation in this approach is considered to be evaluated for all four IEEE standard modes. In [8], a structure of a floating point adder subtractor performing rounding and addition subtraction in parallel is presented. In [9, 10, 11, 12] a floating point multiplier performing rounding and addition in parallel is discussed. However, 9] supports only round to zero mode, which is the easiest ....
W. C. Park, S. W. Lee, O. Y. Kown, T. D. Han, and S. D. Kim, "Floating point adder/subtractor performing IEEE rounding and addition/subraction in parallel," IEICE Trans. Information and Systems, vol. e79-d, no. 4, pp. 297--305, April 1996.
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