Paulin, P. G. and Knight, J. P., "High-Level Synthesis Benchmark Results using a Global Scheduling Algorithm," in Logic and Architecture Synthesis for Silicon Compilers, NorthHolland, pp.211-228, 1989.  Home/Search   Document Not in Database   Summary   Related Articles

....we analyze allocation results for register file and linear topology architectures. 6.2.1 Allocation Results for Multiport Memories. Table 6(a) shows the comparison of allocation results of the EWF example for multiport memory architectures. The 19 control steps scheduling result was borrowed from [34] and used as an input. 2 adders, 1 pipelined multiplier and a two phase clocking scheme were used, which were the same conditions used by the other compared systems. R W notations indicate the number of read write ports in a multiport memory. Table 6(a) indicates that MandM produced better results ....

Paulin, P. G. and Knight, J. P., "High-Level Synthesis Benchmark Results using a Global Scheduling Algorithm," in Logic and Architecture Synthesis for Silicon Compilers, NorthHolland, pp.211-228, 1989.

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