Andrew Seawright, Ulrich Holtmann, Wolfgang Meyer, Barry Pangrle, Rob Verbrugghe, and Joseph Buck. A system for compiling and debugging structured data processing collectors. In Euro-DAC '96, 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....are described at clock cycle level. Actions are specified in VHDL code, similar to the software approaches used by, for instance, YACC [54, 56] 3.2.2. The Synopsys Protocol Compiler The Clairvoyant approach has been developed further into a commercial tool, the Synopsys Protocol Compiler (PC) [63, 64]. It has a graphical user interface for entering the production rules in a hierarchical manner together with their actions. As with Clairvoyant, PC supports actions in a host language (VHDL or Verilog) In addition, Clairvoyant PC has some inbuilt simple data manipulation and communication ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers", Proc. of EuroDAC 96, Geneva, Switzerland, September 1996.

....for each CFSM,forthe RTOS scheduler, and for the interfaces. We assume that existing IP has been adapted to use the POLIS communication protocol, as described below. This adaptation task proved to be very simple in the case study discussed in Section 4, and techniques such as those described in [17] can be used to automate it. In this section we describe each element in detail. 3 3.1 Modeling The Software Tasks The behavioral VHDL simulation model of a piece of software implementing a CFSM is generated automatically using the same mechanism that is used for software synthesis. In this way, ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, et. al. "A System for Compiling and Debugging Structured Data Processing Controllers" EURO-DAC p. 8691, Sept. 1996.

....protocol synthesis tool that specifies the design in a special purpose language ProGram [34] which is based on context free grammar, the synthesizable subset is limited to regular grammar with attributed conditions. The specified protocols are synthesized into hardware. Seawright et al. [29] have a similar approach but instead of grammar they use a graphical version of regular expressions to specify the behaviour. This work has resulted in the commercial tool DALI. It uses a graphical interface for entering the hierarchical production rules, called frames, together with their ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, A system for compiling and debugging structured data processing controllers, Proceedings of the European Design Automation Conference, 1996. DEVICE DRIVER AND DMA CONTROLLER SYNTHESIS 205

....memories etc. communication primitives is a major part of the design effort and is now being treated as a research problem [5] Furthermore, languages and notations that were not main stream in the hardware design community, are being explored to specify communication dominated functionality [6, 7]. Figure 2 magnifies part of the domain lines of the Rugby model and shows the abstraction levels from abstract requirements definitions to a concrete mixed HW SW implementation. It illustrates that domain lines can split when design activities specialise. However, each split must have a ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers", Proceedings of EuroDAC 96, Geneva, Switzerland, September 1996.

....codesign of control dominated applications, for which no memory management needs to be optimized. System synthesis of data flow applications, as SPW BONES from Alta Cadence, and COSSAP from Synopsys, mainly concentrate on synthesis of data flow arithmetic. According to telecom network components, [8,10,12,15] can be considered, but no support for exploration is provided. 13,14] starts from SDL and supports interprocess communication refinement and hardware synthesis of dynamic processes. 6] provides an untimed simulation environment and supports memory management for irregular and dynamic data ....

A. Seawright et al., A system for compiling and debugging structured data processing controllers. EURODAC'96.

....memories etc. communication primitives is a major part of the design effort and is now being treated as a research problem [5] Furthermore, languages and notations that were not main stream in the hardware design community, are being explored to specify communication dominated functionality [6, 7]. Idea Physical system Computation Communication Time Data Development time line High abstraction Low abstraction Figure 4. The Rugby model Electronic System Design Lab 21 March 2000 8 of 19 Figure 5 magnifies part of the domain lines of the Rugby model and shows the abstraction ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers", Proceedings of EuroDAC 96, Geneva, Switzerland, September 1996.

....the software world. In 1992, Seawright et al. presented a tool, called Clairvoyant, that took a grammar based HDL for describing data communication protocols for hardware synthesis [3, 4, 5, 6] Their approach has been developed further into a commercial tool, the Synopsys Protocol Compiler (PC) [7, 8]. In short, they take a grammar based specification and output a distributed Non deterministic FSM described in VHDL that is synthesizable by logic synthesis tools. Actions are specified in a host language (VHDL or Verilog) In addition, Clairvoyant PC has some built in simple data manipulation ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers", Proc. of EuroDAC96, Geneva, Switzerland, September 1996.

....last twenty years, advances in circuit fabrication technology have increased device densities and as a consequence, they have increased design complexity. To manage continuously emerging tasks, designers have moved towards higher levels of abstraction [31] and language based design descriptions [14, 16, 27, 28, 21], which are closer to the way they conceive their work. However, each design must be described, eventually, at the lowest level (e.g. layout masks) in order to be fabricated. The transformation from one level of abstraction to the next is performed by various synthesis processes. High level or ....

....for other application domains. With a recent extension [20] PRO GRAM has been used for the automatic generation of VHDL test benches for communication interfaces, used for design validation through simulation. Similar to PRO GRAM was the extension of Clairvoyant presented by Seawright et al. [28], the system called Dali. Dali uses a graphical hierarchical representation to describe systems that process structured data streams or handle structured control protocols, i.e. telecommunications protocols or compression algorithms. Compilation techniques are used to transform this specication ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck. A system for compiling and debugging structured data processing controllers. In European Design Automation Conference with EURO-VHDL, pages 8691. ACM/IEEE, 1996.

....built from such grammar specification. Grammar rules can be annotated with actions to be taken when a particular grammar rule is recognized. This is the principle of grammar based hardware synthesis. There are a number of grammar based hardware synthesis systems in the academic world [1, 2, 3, 4, 5]. 2] is a commercial version of [1] Though these systems are based on the same essential idea, they differ in their syntax, synthesis strategy, target architecture and the methodology for using them. Functional Model Bit true Model Rate true Model Cycle true Model Figure 1. The four levels ....

....from such grammar specification. Grammar rules can be annotated with actions to be taken when a particular grammar rule is recognized. This is the principle of grammar based hardware synthesis. There are a number of grammar based hardware synthesis systems in the academic world [1, 2, 3, 4, 5] [2] is a commercial version of [1] Though these systems are based on the same essential idea, they differ in their syntax, synthesis strategy, target architecture and the methodology for using them. Functional Model Bit true Model Rate true Model Cycle true Model Figure 1. The four levels of ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers ", in Proc. of EuroDAC96, Geneva, Switzerland, September 1996.

....protocol processor. Seawright et. all present a grammar based tool called Clairvoyant in [7] 8] The tool uses a grammar based hardware description language to specify and synthesize digital synchronous hardware systems. The tool was later further developed into a commercial tool, then called DALI[9], now called the Synopsys Protocol Compiler [10] In [12] the ProGram language was introduced together with a methodology for performing design space exploration of the input port sizes. The methodology was extended in [13] with two simple schedule algorithms for scheduling of output ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers", in Proc. of EuroDAC `96, Geneva, Switzerland, September 1996.

....interfaces in practice. Both, however, are poorly suited for this task, since they do not exploit any particular characteristics of interfacing. Models with explicit concurrency, sequencing and choice, such as synchronous PNs [3] synchronous languages [29, 30] or Regular Grammars (RGs) [53, 50] can be used more efficiently in this case. In particular, RGs have been used in several recent approaches to interface design. A Regular Grammar (or, equivalently, a Regular Expression) denotes a regular language, and hence can be recognized generated by a Finite State Machine. An RG is ffl ....

....symbol, defined by a combination of RGs by sequencing, alternative and bounded or unbounded repetition. The basic idea is that protocol specifications, such as the structure of an ATM cell, are easier to model with an RG than with an HDL. For example, the ATM frame for one cell (from [53]) at the top level is defined by the following regular grammar. Parentheses are used for grouping, separates a non terminal from its definition, denotes sequencing, denotes concurrency (within the same clock cycle) # denotes alternative, n denotes repetition n times and 3 ....

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A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, and J. Buck. A system for compiling and debugging structured data processing controllers. In Proceedings of the European Design Automation Conference (EURO-DAC), pages 86--91, September 1996.

....memories etc. communication primitives is a major part of the design effort and is now being treated as a research problem [7, 8] Furthermore, languages and notations that were not main stream in the hardware design community, are being explored to specify communication dominated functionality [9, 10] The structural and physical domains of the Y chart are merged into this domain because movement from a topological to a layout model is considered as a refinement operation, not an inter domain movement. The layout level is based on principles of geometry and uses physical units to describe ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers", Proceedings of EuroDAC 96, September 1996.

....PSM to model interfaces. berg et al. present a communication protocol synthesis tool that specifies the design in a special purpose language ProGram [12] which is based on context free grammar, the synthesizable subset is limited to regular grammar with attributed conditions. Seawright et al. [9] have a similar approach but instead of grammar they specify the behaviour with a graphical version of regular expressions. Table 1 shows a comparison between some of the approaches described above and the extended version of ProGram presented in this paper. The table shows that interfaces ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers", In Proc. of Euro-DAC, Sept. 1996.

....communication interfaces and other control dominated circuits including Communication Protocols. In Clairvoyant a design entity with a single process and a well defined boundary and interface is specified. All inputs and outputs in the design entity are exactly described at clock cycle level. DALI [6], is a commercial system based on the Clairvoyant system. It uses a graphical interface for entering the production rules, called frames, in a hierarchical manner together with their actions. As with Clairvoyant, DALI supports actions in a host language (VHDL or Verilog) In addition, DALI has ....

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers", in Proc. of EuroDAC `96, Geneva, Switzerland, September 1996.

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Andrew Seawright, Ulrich Holtmann, Wolfgang Meyer, Barry Pangrle, Rob Verbrugghe, and Joseph Buck. A system for compiling and debugging structured data processing collectors. In Euro-DAC '96, 1996.

No context found.

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers," in Proceedings of the European Design Automation Conference 1996.

No context found.

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, J. Buck, "A system for compiling and debugging structured data processing controllers," in Proc. Euro DAC., pp. 86-91, Sept. 1996.

No context found.

Andrew Seawright, Ulrich Holtmann, Wolfgang Meyer, Barry Pangrle, Rob Verbrugghe, and Joseph Buck. A system for compiling and debugging structured data processing collectors. In Euro-DAC '96, 1996.

No context found.

A. Seawright, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe, and J. Buck, "A System for Compiling and Debugging Structured Data Processing Controllers", in Proc. of the European Design Automation Conference 1996, Geneva, Switzerland, 1996, pp. 86-91.

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