N. Nicolici and B. Al-Hashemi, "Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circits," in Proc. Design, Automation and Test in Europe (DATE'00), pp. 715722, 2000. Home/Search Document Details and Download
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A Unified Approach to Reduce SOC Test Data Volume, Scan.. - Chandra, Chakrabarty (2003) (Correct)
....and c) tester based. 1) Structural methods: These methods, which do not address test data volume or testing time, are based on the following design techniques. Gated scan chains: These refer to schemes that use gating techniques to clock portions of the scan chain during scan operation [15] [17] In [15] shift registers are used to gate portions of the scan chain during shifting while counters are used for gating in [16] A decoder multiplexer based architecture for gating scan chains has also been proposed in [17] Modified test pattern generator (TPG) Test generation ....
....tester based. 1) Structural methods: These methods, which do not address test data volume or testing time, are based on the following design techniques. Gated scan chains: These refer to schemes that use gating techniques to clock portions of the scan chain during scan operation [15] 17] In [15], shift registers are used to gate portions of the scan chain during shifting while counters are used for gating in [16] A decoder multiplexer based architecture for gating scan chains has also been proposed in [17] Modified test pattern generator (TPG) Test generation circuits can be ....
N. Nicolici and B. M. Al-Hashimi, "Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits," in Proc. IEEE/ACM Design, Automation, Test Eur. Conf., Mar. 2000, pp. 715--722.
Power Minimisation Techniques for Testing Low Power VLSI Circuits - Nicolici (2000) (2 citations) (Correct)
....or volume of test data when compared to standard scan method described in Section 1.2. The technique is test set dependent and it is applicable to small to medium sized scan sequential circuits at the logic level of abstraction. Chapter 4 introduces a new test set independent technique [143] applicable to large scan sequential circuits and shows how with low overhead in test area and volume of test data, and with no penalty in test application time, test efficiency, or performance, considerable savings in power dissipation during test application in large scan sequential circuits is ....
....of low overhead in computational time. Finally, conclusions and directions for future research are given in Chapter 7. The previously outlined contributions in Chapters 3, 4, 5, and 6, and summarised in the final Chapter 7 have resulted in original work published or submitted for publication [139, 140, 141, 142, 143, 144, 145]. Motivation and Previous Work Personal mobile communications and portable computing systems are the fastest growing sectors of the consumer electronics market. The electronic devices at the heart of such products need to dissipate low power, in order to conserve battery life and meet packaging ....
N. Nicolici and B.M. Al-Hashimi. Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits. In Proc. IEEE/ACM Design Automation and Test in Europe (DATE 2000.
Power Conscious Test Synthesis and Scheduling for BIST RTL.. - Nicolici, Al-Hashimi (2000) (3 citations) Self-citation (Nicolici Al-hashimi) (Correct)
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N. Nicolici and B. Al-Hashimi, "Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits," in Proc. IEEE/ACM Design Automation and Test in Europe (DATE 2000), (Paris, France), pp. 715--722, March 2000.
RL-Huffman Encoding for Test Compression and Power.. - Nourani, Tehranipour (1995) (Correct)
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N. Nicolici and B. Al-Hashemi, "Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circits," in Proc. Design, Automation and Test in Europe (DATE'00), pp. 715722, 2000.
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