R. Sankaralingam, R. Oruganti and N. A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation," in Proc. VLSI Test Symp. (VTS'00), pp. 35-40, 2000.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....2) Algorithmic methods: These include automatic test pattern generation (ATPG) under power constraints, techniques based on test data compression, and test scheduling algorithms. ATPG techniques: ATPG techniques for generating vectors that lead to low power testing are described in [23] and [26]. However, while these techniques provide reduction in power consumption, they do not lead to any appreciable decrease in test data volume. Test data compression: Test generation for low power scan testing usually leads to an increase in the number of test vectors [23] On the other hand, ....

....any appreciable decrease in test data volume. Test data compression: Test generation for low power scan testing usually leads to an increase in the number of test vectors [23] On the other hand, static compaction of scan vectors causes significant increase in power consumption during testing [26]. While compacted vectors are useless if they exceed power constraints, uncompacted vectors cannot be used as they require excessive tester memory. Power minimization based on test data compression was first presented in [34] Test scheduling: Test scheduling techniques for system integration ....

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R. Sankaralingam, R. R. Oruganti, and N. A. Touba, "Static compaction techniques to control scan vector power dissipation," in Proc. VLSI Test Symp., 2000, pp. 35--40.

....the low transition random test pattern generator (LT RTPG) proposed in [192] where neighbouring bits of the test vectors are assigned identical values in most test vectors. A simple and fast procedure to compact scan vectors as much as possible without exceeding power dissipation was proposed in [172]. All the previous scan based BIST methods [46, 61, 172, 182, 192] introduce test area overhead and or further performance degradation when compared to scan DFT methodology. A different technique [49] based on test vector and scan cell ordering minimises power dissipation in full scan sequential ....

....(LT RTPG) proposed in [192] where neighbouring bits of the test vectors are assigned identical values in most test vectors. A simple and fast procedure to compact scan vectors as much as possible without exceeding power dissipation was proposed in [172] All the previous scan based BIST methods [46, 61, 172, 182, 192] introduce test area overhead and or further performance degradation when compared to scan DFT methodology. A different technique [49] based on test vector and scan cell ordering minimises power dissipation in full scan sequential circuits without any overhead in test area or performance ....

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R. Sankaralingam, R.R. Oruganti, and N.A. Touba. Static compaction techniques to control scan vector power dissipation. In Proc. of the 18th IEEE VLSI Test Symposium, pages 35--40, 2000.

....The authors are with the Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708 USA (e mail: achandra ee.duke.edu) Publisher Item Identifier S 0278 0070(02)02846 4. built in self test (BIST) 4] 7] and techniques for minimizing power during scan testing [8] [10]. Power consumption and the resulting heat dissipation are especially important for SOCs since test scheduling techniques and test access architectures for system integration attempt to reduce testing time by applying scan BIST vectors to several cores simultaneously [11] 15] Therefore, it is ....

....scan testing and reduced test data volume appear to be irreconcilable. Test generation for low power scan testing usually leads to an increase in the number of test vectors [8] On the other hand, static compaction of scan vectors causes significant increase in power consumption during testing [10]. The compacted vectors are rendered useless if they exceed power constraints. Clearly, uncompacted vectors cannot be used since they require excessive tester memory. This problem is addressed in a recent paper on power constrained static compaction of scan vectors [10] However, while [10] ....

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R. Sankaralingam, R. R. Oruganti, and N. A. Touba, "Static compaction techniques to control scan vector power dissipation," in Proc. IEEE VLSI Test Symp., 2000, pp. 35--40.

....inordinately. The increases in turn boost test application cost by necessitating prolonged utilization of increasingly expensive testers. A number of schemes have been proposed for test data volume reduction of scan based deterministic test by improving the effectiveness of test compaction [2, 4, 13, 14, 17] and compression schemes [7, 8, 9, 10] While compaction schemes try to reduce the number of patterns generated without compromising fault coverage levels, compression schemes in turn target reduction of the storage requirements of the compacted test patterns. Additionally, shifting the ....

....prior specific permission and or a fee. DAC 2001, June 18 22, 2001, Las Vegas, Nevada, USA. Copyright 2001 ACM 1 58113 297 2 01 0006 . 5.00. ulation is performed to drop the faults that are detected by the test vector. Though a number of schemes have been proposed to compact test vectors [2, 4, 13, 14, 17], either statically or dynamically, the resultant test sets still remain inordinately large. While randomly setting the unspecified bits improves the effectiveness of fault dropping, it reduces the effectiveness of compression schemes as compression algorithms are known to perform poorly on ....

R. Sankaralingam, R. Oruganti, and N. A. Touba. Static compaction techniques to control scan vector power dissipation. In VLSI Test Symposium, pages 35--40, 2000.

....low transition random test pattern generator (LT RTPG) proposed in [31] where neighbouring bits of the test vectors are assigned identical values in most test vectors. A simple and fast procedure to compact scan vectors as much as possible without exceeding power dissipation has been proposed in [32]. All the previous scan based BIST techniques [28 32] introduce test area overhead and or further performance degradation when compared to scan DFT methodology. A different technique [12] based on test vector and scan latch ordering minimizes power dissipation in full scan sequential circuits ....

....proposed in [31] where neighbouring bits of the test vectors are assigned identical values in most test vectors. A simple and fast procedure to compact scan vectors as much as possible without exceeding power dissipation has been proposed in [32] All the previous scan based BIST techniques [28 32] introduce test area overhead and or further performance degradation when compared to scan DFT methodology. A different technique [12] based on test vector and scan latch ordering minimizes power dissipation in full scan sequential circuits without any overhead in test area or performance ....

[Article contains additional citation context not shown here]

R. Sankaralingam, R. R. Oruganti, and N. A. Touba, "Static compaction techniques to control scan vector power dissipation," in Proc. of the 18th IEEE VLSI Test Symposium, 2000.

....application [1] A number of techniques to control power consumption in test mode have been presented in the literature. These include test scheduling algorithms under power constraints [2] low power built in self test (BIST) 3, 4] and techniques for minimizing power during scan testing [5, 6, 7]. Power consumption is especially important for SOCs since test scheduling techniques for system integration attempt to reduce testing time by applying scan BIST vectors to several cores simultaneously [8, 9] Therefore, it is extremely important to decrease power consumption while testing the IP ....

....scan testing and reduced test data volume appear to be irreconcilable. Test generation for low power scan testing usually leads to an increase in the number of test vectors [5] On the other hand, static compaction of scan vectors causes significant increase in power consumption during testing [7]. The compacted vectors are rendered useless if they exceed power constraints. Clearly, uncompacted vectors cannot be used since they require excessive tester memory. This problem is addressed in a recent paper on power constrained static compaction of scan vectors [7] However, while [7] provides ....

[Article contains additional citation context not shown here]

R. Sankaralingam, R. R. Oruganti and N. A. Touba, "Static compaction techniques to control scan vector power dissipation", Proc. VTS, pp. 35-40, 2000.

.... in [15] Regularity of multiplier modules and linear sized test set required to achieve high fault coverage lead to efficient low power BIST implementations [16] To minimize power dissipation in scan BIST sequential circuits during test application numerous techniques have been proposed recently [17 20]. To minimize shifting power dissipation, test vector inhibiting techniques proposed for combinational circuits are extended to scan sequential circuits [17] In [18] the test vector inhibiting technique is extended where the modules and modes with the highest power dissipation are identified, and ....

....In the low transition random test pattern generator (LT RTPG) proposed in [19] neighbouring bits of the test vectors are assigned identical values in most test vectors. A simple and fast procedure to compact scan vectors as much as possible without exceeding power dissipation has been proposed in [20]. It should be noted that techniques proposed for reducing power dissipation in standard scan design for test (DFT) methodology [21 25] can equally be applied to scanBIST environment subject to minor modifications. While techniques for power minimization at logic level yield modest savings they ....

R. Sankaralingam, R. R. Oruganti, and N. A. Touba, "Static compaction techniques to control scan vector power dissipation," in Proc. of the 18th IEEE VLSI Test Symposium, 2000.

....to actually find the number of circuit elements that switch when a vector is scanned in. However this procedure takes a very long execution time and is thus very expensive. Instead, in this paper to estimate the scan in or the scan out power, we use the weighted transitions metric proposed by [Sankaralingam 00] In their paper, they have found that the sum of average weighted scan in transitions and the average weighted scan out transitions is fairly closely correlated to the average number of circuit elements that make transitions in the CUT. The weighted transitions metric model can be explained as ....

....while being scanned in, Transition 2 only dissipates power at the first scan cell. Thus when a test vector is being scanned in, the number of scan cell transitions caused by a particular transition in that vector would depend on the position of the transition in the scan vector. According to [Sankaralingam 00] the weight assigned to a transition is the difference between the size of the scan chain and the position in the vector in which the transition occurs. The number of weighted transitions is given by: Weighted Transitions = S (Size of Scan Chain Position of Transition) Figure 1. Transitions ....

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R. Sankaralingam, R. Oruganti and N. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation", IEEE VLSI Test Symposium, pp. 35-42, 2000.

....in the scan chain. The best way to estimate power during scan testing would be to do actual circuit simulation to find the number of circuit elements that switch when a vector is scanned in. However this procedure is very time intensive. Instead, we use the weighted transitions metric proposed by [9] to estimate the scan in or scan out power. According to this model, the sum of average weighted scan in transitions and scan out transitions is fairly closely correlated to the average number of circuit elements that make transitions in the CUT, if the weight assigned to a transition is the ....

.... transitions and scan out transitions is fairly closely correlated to the average number of circuit elements that make transitions in the CUT, if the weight assigned to a transition is the difference between the size of the scan chain and the position in the vector in which the transition occurs [9]. 3. Estimation of Area overhead In an algorithm that re orders the scan chains to reduce the power dissipation, the main concern is whether the reordering increases the area overhead of the circuit. We have used two terms that give a measure of the area overhead. One measure of the area ....

R. Sankaralingam, R. Oruganti and N. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation", Proc. of IEEE VLSI Test Symposium, pp. 3542, 2000.

....reducing the average power dissipation per clock cycle over the entire test session. Previous work in low power scan testing has mostly focused on the problem of controlling heat dissipation by reducing the average power dissipation [Chou 94] Wang 94, 97ab, 99] Dabholkar 98] Girard 99a] Sankaralingam 00, 01] Chandra 01] Some designfor test (DFT) techniques reduce peak power in addition to average power. In [Hertwig 98] and [Gerstendrfer 99] logic is added to hold the output of the scan cells at a constant value during scan shifting thereby reducing power dissipation. This approach greatly ....

....and then repeatedly divided as necessary. The number of additional scan vectors that results from partitioning the fault set can be reduced by static compaction. The static compaction procedure can be constrained so that the number of transitions in the merged vector never exceeds some threshold [Sankaralingam 00] For example, suppose that bitstripping scan vector t resulted in a vector that had 100 transitions in the specified bits (the X s are assumed to be filled with MT fill) However, by partitioning F t into 8 subsets, the resulting 8 vectors after bit stripping all have fewer than 50 transitions ....

Sankaralingam, R., R.R. Oruganti, and N.A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation", Proc. of VLSI Test Symp., pp. 35-40, 2000.

....reducing the average power dissipation per clock cycle. 1. 1 Previous Work Previous work in low power scan testing has mostly focused on the problem of controlling heat dissipation by reducing the average power dissipation during scan testing [Wang 94, 97ab, 99] Dabholkar 98] Girard 99a] Sankaralingam 00, 01] see [Bonhomme 02] for a survey) These techniques are applicable in cases where the heat dissipation during testing exceeds the package s limit. Some design for test (DFT) techniques reduce peak power in addition to average power. In [Whetsel 00] an adapted scan chain architecture that ....

....for the full scan versions of the circuits using a commercial automatic test pattern generation (ATPG) tool. The unspecified values in the test cubes from the ATPG tool were filled such that the number of transitions during scan in would be as low as possible (i.e. minimum transition fill [Sankaralingam 00] Simulation was done to identify the violating cycles and the power reduction due to the candidate test points. A commercial ILP solver was used to select test points. Simulation and the ILP solver were used together to eliminate all violating cycles as described in Sec. 5. Test points were ....

Sankaralingam, R., R.R. Oruganti, and N.A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation", Proc. of VLSI Test Symposium, pp. 35-40, 2000.

.... Low power BIST techniques were presented in [Wang 97a] Hertwig 98] Wang 99] Gerstendrfer 99] Girard 99, 00] Techniques for minimizing power dissipation when testing combinational circuits were presented in [Wang 94] Dabholkar 98] and for scan circuits in [Wang 97b] Dabholkar 98] Sankaralingam 00] Whetsel 00] The focus of this paper is on the problem of minimizing power dissipation during scan testing. Wang 97b] modifies the controllability and observability cost functions in PODEM [Goel 81] to find a set of scan vectors that minimizes test power. Sankaralingam 00] describes a ....

....[Dabholkar 98] Sankaralingam 00] Whetsel 00] The focus of this paper is on the problem of minimizing power dissipation during scan testing. Wang 97b] modifies the controllability and observability cost functions in PODEM [Goel 81] to find a set of scan vectors that minimizes test power. Sankaralingam 00] describes a guided algorithm for static compaction of scan vectors to minimize switching activity. Dabholkar 98] proposes heuristic algorithms for test vector ordering and scan chain ordering that minimize average power during scan testing. Whetsel 00] describes an adapted scan chain ....

Sankaralingam, R., R.R. Oruganti, and N.A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation", Proc. of VLSI Test Symposium, pp. 35-40, 2000.

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R. Sankaralingam, R. Oruganti and N. A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation," in Proc. VLSI Test Symp. (VTS'00), pp. 35-40, 2000.

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R. Sankaralingam, R. Oruganti and N. A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation," in Proc. VLSI Test Symp. (VTS'00), pp. 35-40, 2000.

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R. Sankaralingam, R. R. Oruganti, , and N. A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation," in Proceedings IEEE VLSI Test Symposium (VTS), pp. 35--40, Apr. 2000.

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