J. Monteiro, S. Devadas, and A. Ghosh, "Sequential logic optimization for low power using input-disabling precomputation architectures," IEEE Trans. Computer-Aided Design, vol. 17, pp. 279--284, Mar. 1998. Home/Search Document Details and Download
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Synthesis of Power-Managed Sequential Components.. - Benini, De.. (Correct)
....other kinds of behaviors than just idleness, it may Fig. 4. Symbolic kernel extraction algorithm. potentially provide more prominent opportunities for power reduction and it can be applied to sequential blocks for which clock gating is ineffective. Precomputation based power optimization [23] [24] pushes the clock gating concept even further. The simple idleness detection logic is replaced by more complex precomputation function that can either detect partial idle conditions (i.e. conditions in which only part of the original circuit needs to be active to compute correct output and ....
J. Monteiro, S. Devadas, and A. Ghosh, "Sequential logic optimization for low power using input-disabling precomputation architectures," IEEE Trans. Computer-Aided Design, vol. 17, pp. 279--284, Mar. 1998.
Power Minimisation Techniques for Testing Low Power VLSI Circuits - Nicolici (2000) (2 citations) (Correct)
....devices at the heart of such products need to dissipate low power, in order to conserve battery life and meet packaging reliability constraints. Low power design in terms of algorithms, architectures, and circuits has received significant attention and research input over the last decade [8, 116, 131, 158, 161, 179]. Although low power design methodologies will solve the problem of designing complex, low power digital very large scale integrated (VLSI) circuits, such circuits will still be subject to manufacturing defects. It was implicitly assumed that traditional design for testability (DFT) methodologies ....
J. Monteiro, S. Devadas, and A. Ghosh. Sequential logic optimization for low power using input disabling precomputation architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 17(3):279--284, March 1998.
Minimisation of Power Dissipation During Test.. - Nicolici.. (2000) (1 citation) (Correct)
....[1] and has been investigated at different design hierarchy levels. High level power minimisation techniques [2, 3, 4] trade off throughput, area and power dissipation during scheduling, allocation and binding. At the logic level, two successful power management techniques, based on precomputation [5, 6] and guarded evaluation [7] have been presented. While the above research has outlined solutions for minimising power dissipation during the normal (functional) mode of operation, it is essential to examine the power dissipation during the test mode of operation. It was outlined in [8] that power ....
MONTEIRO, J., DEVADAS, S., and GHOSH, A.: 'Sequential logic optimization for low power using input disabling precomputation architectures,' IEEE Transactions on CAD, 1998, 17(3), pp. 279--284
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