A. V. Curiger, H. Bonnenberg, and H. Kaeslin. Regular VLSI Architectures for Multiplication Modulo (2  Home/Search Document Not in Database Summary Related Articles Check |
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Tradeoffs in Parallel and Serial Implementations of the .. - Cheung, Tsoi, Leong.. (2001) (1 citation) (Correct)
....acceptable. These features make deeply pipelined implementations possible. 6 O.Y.H. Cheung et al. 2.1 Multiplication Modulo 2 n 1 Of the basic operations used in the IDEA algorithm, multiplication modulo 2 16 1 is the most complicated and occupies most of the hardware. Curiger et al. [20] described and compared several VLSI architectures for multiplication modulo 2 n 1 and found that an architecture proposed by Meier and Zimmerman [21] using modulo 2 n adders with bit pair recoding offers the best performance. The C code for the multiplication modulo 2 16 1 operation ....
A. V. Curiger, H. Bonnenberg, and H. Kaeslin, "Regular VLSI architectures for multiplication modulo 2 n + 1," IEEE Journal of Solid-State Circuits, vol. 26, pp. 990--994, July 1991.
IDEA as a Benchmark for Reconfigurable Computing - Caspi, Weaver (1996) (3 citations) (Correct)
....has value 2 16 . This representation relies on the cryptographic principle that every operation must be reversible, so a number should never be multiplied by 0. Although it might seem that the modulo operation complicates matters, there is a relatively easy way to perform the modulo operation[4] based on the following arithmetic identities: x mod(2 n 1) x mod(2 n ) Gamma x div(2 n ) mod(2 n 1) 1) x mod(2 n 1) ae (x mod(2 n ) Gamma (x div(2 n ) 1 if x div(2 n ) x mod(2 n ) x mod(2 n ) Gamma (x div(2 n ) otherwise (2) Equation 2 maps ....
A. V. Curiger, H. Bonnenberg, and H. Kaeslin. Regular VLSI Architectures for Multiplication Modulo (2 n + 1). IEEE Journal of Solid-State Circuits, 26(7):990--994, July 1991.
A Bit-Serial Implementation of the International Data.. - Leong, Cheung, Tsoi.. (2000) (6 citations) (Correct)
....These feature make the algorithm suitable to be implemented as a deep bit serial pipeline. 2.1 Multiplication Modulo 2 n 1 Of the basic operations used in the IDEA algorithm, multiplication modulo 2 16 1 is the most complicated and occupies most of the hardware. Curiger et al. [15] described and compared several VLSI architectures for multiplication modulo 2 n 1 and found that an architecture proposed by Meier and Zimmerman [16] using modulo 2 n adders with bit pair recoding offers the best performance. The pseudocode for the modular multiplication operation by ....
A. V. Curiger, H. Bonnenberg, and H. Kaeslin, "Regular VLSI architectures for multiplication modulo 2 n +1," IEEE Journal of Solid--State Circuits, vol. 26, pp. 990--994, July 1991.
CryptoBooster: A Reconfigurable and Modular.. - Mosanya.. (1999) (3 citations) (Correct)
....the importance of the combinatorial delay and area consumption of the multiplication modulo (2 16 1) units which are crucial to the entire system. These units are the limiting factor to obtain high data throughput. Various methods of implementing such a multiplication are investigated in [3, 5, 10,15, 16]. The VINCI implementation uses a modied Booth recording multiplication and fast carry select additions for the nal modulo correction [17] In general, for larger words, ROM based solutions using lookup tables require large ROMs. In a recent paper, Zimmermann [16] presents an eOEcient VLSI ....
A. Curiger, H. Bonnenberg, and H. Kaeslin. Regular VLSI-architectures for multiplication modulo (2 n + 1). IEEE Journal of Solid-State Circuits, 26(7):990994, July 1991.
VLSI Design Methodologies For Computing X mod m - Sivakumar, Dimopoulos (1995) (Correct)
....revolutionary advances in microelectronics. The RNS is a carry free number system that has the fundamental ability to support a high degree of parallelism, modularity and regularity. These features can be exploited in VLSI to build high speed digital circuits for applications in signal processing [1, 2]. Several algorithms for Fourier transforms, convolution, digital filtering, cryptography and error control coding [3] 5] require hardware circuits such as adders, multipliers and random number generators that involve arithmetic modulo operations [6] 8] In this work, we propose and analyze VLSI ....
A. V. Curiger, H. Bonnenberg, and H. Kaeslin, "Regular VLSI Architectures for multiplication Modulo (2 n + 1)", IEEE J. Solid-State Circuits, 1991, 26 (7), pp. 990-994.
Efficient VLSI Implementation of Modulo (2^n ± 1).. - Zimmermann (1999) (Correct)
....1 c in 2 c in 3 c out 1 c out 2 c out 3 c in 4 c out 4 (b) Figure 6. a) Linear and (b) tree structured (8,2) compressor. 3. Modulo multiplication For modulo multiplication, P = X Delta Y mod (2 n Sigma 1) 23) various ROM based solutions using table lookup have been proposed and compared[10, 3]. Sophisticated methods exist to reduce the table sizes by combining smaller table lookups with simple arithmetic operations, such as additions. For word lengths larger than eight bits, however, these solutions still require prohibitively large ROMs or many clock cycles for evaluation. For ....
....or many clock cycles for evaluation. For high performance modulo multiplication, dedicated multipliers are required which can be implemented as combinational or pipelined circuits. Solutions based on ordinary integer multiplication with subsequent modulo correction using adders are proposed in [3, 5]. A modulo (2 n 1) multiplier architecture with modulo reduced, Booth recoded partial products and with concurrent modulo reduction during carry save addition is proposed in [3] and improved in [9] It is shown in [13] that modulo (2 n 1) multipliers with highly regular modulo carry save ....
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A. V. Curiger, H. Bonnenberg, and H. Kaeslin. Regular VLSI architectures for multiplication modulo (2 n + 1). IEEE J. Solid-State Circuits, 26(7):990--994, July 1991.
A 177 Mbit/s VLSI Implementation of the.. - Zimmermann.. (1993) Self-citation (Curiger Bonnenberg Kaeslin) (Correct)
....2 16 1 Combinational delay and area consumption of the multiplication modulo (2 16 1) unit are crucial to the entire chip architecture and to the maximum attainable data throughput rate. Various methods of implementing such a dedicated multiplication unit were investigated and compared [7]. Table lookup based solutions and an ordinary multiplication with subsequent modulo correction both resulted in overly high computation time and area. Therefore a customlayout realization was chosen using a computation scheme with stepwise modulo reduction. A modified Booth recoding ....
A. Curiger, H. Bonnenberg, and H. Kaeslin. Regular VLSI-architectures for multiplication modulo (2 n + 1). IEEE Journal of Solid-State Circuits, 26(7):990--994, July 1991.
Some Modular Adders and Multipliers for Field Programmable Gate.. - Beuchat (2003) (Correct)
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A. V. Curiger, H. Bonnenberg, and H. Kaeslin. Regular VLSI Architectures for Multiplication Modulo (2
Some Modular Adders and Multipliers for Field Programmable Gate.. - Beuchat (2002) (Correct)
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A. V. Curiger, H. Bonnenberg, and H. Kaeslin. Regular VLSI Architectures for Multiplication Modulo (2 + 1). IEEE Journal of Solid-State Circuits, 26(7):990994, 1991.
An Efficient Tree Architecture for Modulo 2n+1 Multiplication - Wang, al. (1996) (1 citation) (Correct)
No context found.
A. V. Curiger, H. Bonnenberg and H. Kaeslin: "Regular VLSI architecture for multiplication modulo (2 +1)", IEEE J. Solid-State Circuits, vol. 26, pp. 990-994, 1991
Hardware Software Tri-Design Of Encryption For Mobile.. - Mencer, Morf, Flynn (12 citations) (Correct)
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A. Curiger, H. Bonnenberg, H. Kaeslin, Regular VLSI-architectures for multiplication modulo (2 n + 1), IEEE Journal of Solid-State Circuits, July 1991.
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