L.M Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEEE Transactions on Computers, C-27(10):866--872, December 1978.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....implementations that select positive broadcast as the method of distributing tuples must also select a coherence protocol as tuples are duplicated on all nodes. The available protocols are essentially the same as those developed by the cache coherency research (for background one can start with [28, 13, 1, 15], and for more current research see [14, 30] Bjornson [6] noted the advantages of replicating read only tuples, thus implementations that provide this optimization must also decide on an appropriate coherence protocol. Tuple Transfer Protocol Tuple transfer is the movement of a tuple among ....

Lucien M. Censier and Paul Feautrier. A new solution to coherence problems in multicache systems. IEEE Transactions on Computers, C-27(12):1112--1118, Dec 1978.

.... it is relatively straight forward to add a caching system on top of SUDS, and in fact a software based L1 cache was implemented on top of an earlier version of SUDS [128] The basic idea behind adding caching on top of SUDS would be to implement a standard directory based cache coherence scheme [21, 10, 2]. The key to a directory based cache coherence scheme is that the directory is guaranteed to see all the traffic to a particular memory location, and in the same global order that is observed in all other parts of the system. Thus, the directory controller can simply forward the list of requests ....

....out the similarity between cache coherence schemes and coherence control in transaction processing. The Liquid system used a bus based protocol similar to a snooping cache coherence protocol [47] SUDS uses a scalable protocol that is more similar to a directory based cache coherence protocol [21, 10, 2] with only a single pointer per entry, sometimes referred to as a Dir1B protocol. The ParaTran system for parallelizing mostly functional code [116] was another early proposal that relied on speculation. ParaTran was implemented in software on a shared memory multiprocessor. The protocols were ....

Lucien M. Censier and Paul Feautrier. A new solution to coherence problems in multicache systems. IEEE Transactions on Computers, C-27(12):1112--1118, December 1978.

....the local cache (see Figure 5) Any actions required by the cache coherency protocol then takes place as with normal caches. In a multiprocessor system where each processor has a local cache there is a problem of maintaining identical views of the logically shared memory from all the processors [1]. Specifically, in order for the caches to be transparent to the software, the system is often required to be memory coherent, i.e. the memory system is required to ensure that the value returned on a load is always the value given by the latest store instruction with the same address [1] A ....

.... [1] Specifically, in order for the caches to be transparent to the software, the system is often required to be memory coherent, i.e. the memory system is required to ensure that the value returned on a load is always the value given by the latest store instruction with the same address [1]. A multiprocessor system in which our FIFO CAMs are used with the caches is not memory coherent. Specifically, a load executed by one processor cannot return the latest value written to the address by a store from another processor until the value stored propagates to the head of the ....

Lucien M. Censier and Paul Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Transactions on Computers C-27(12), pp. 1112-1118 (December 1978).

....contention in the interconnection network. Figure 1.2 shows the modified machine, incorporating a cache with each processor. Unfortunately, the existence of multiple caches in a shared memory environment can lead to data inconsistencies. This is commonly referred to as the cache coherence problem [5]. Any system allowing multiple copies of a data item to exist at the same time must solve this problem. Various hardware schemes have been proposed to solve the coherence problem. They can be classified as either snooping cache protocols or directory based protocols. Snooping protocols [3] ....

....protocols. Snooping protocols [3] require inexpensive broadcast, limiting their scalability. Directory based protocols do not impose any restrictions on the interconnection network and, therefore, can be used in large scale parallel machines. Examples of such protocols are the fullmap scheme [5, 12], the chained list scheme [6] the limited copy scheme [6, 7] and the hierarchical protocols [11, 18] Two major classes of large scale shared address space multiprocessors have emerged in the literature. These are non uniform memory access machines (NUMA) 17, 14, 7] and cache only memory ....

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L. Censier and P. Feautrier, "A new solution to the coherence problem in multicache systems," IEEE Transactions on Computers, pp. 1112 -- 1118, 1978.

....we can experiment with various message scheduling policies to resolve contention among multiple messages trying to acquire the same channel, link allocation policies among virtual channels, buffer sizes, and memory management policies. Also, we implement a directory based cache coherence protocol [10] in our simulator and realistic synchronization techniques [11] Consideration of all the network parameters and their effect on the system performance is beyond the scope of this paper because of the time and space constraints. Here, we will limit ourselves to two switching techniques packet ....

....memory controller, and a network interface, as shown in Fig 1(b) The nodes are connected to a switch through the network interface. The input and output links of a switch connect to other switches to form the multistage IN. The system implements a full map directory based cache coherence scheme [10] which will be described later. The processors are assumed to have only a single thread and no prefetching of cache blocks is performed. The system is assumed to be sequentially consistent, which means that there are no write buffers and cache misses on load or store operations block the ....

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L. M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Transactions on Computers, vol. C-27, no. 12, pp. 1112--1118, December 1978.

....limited bandwidth provided by a bus and also due to the limited number of processors that can be attached to a single bus. A directory based protocol avoids this problem by not requiring a broadcast medium. Several directory based cache coherence protocols have been proposed in the literature [3, 4, 5, 6]. In all of these, each memory block is mapped to a home node which keeps a directory of the caches having a copy of this block. The directory entry for a block consists of the state of the block and a presence bit vector indicating the caches with a copy of the block. The scalability of such a ....

L. M. Censier and P. Feautrier, "A new solution to coherence problems in multicache systems," IEEE Trans. Comput., vol. C-27, no. 12, pp. 1112--1118, Dec. 1978.

....schemes attempt to address the issue of storage overhead due to directory to make the directory based schemes scalable. Other schemes reviewed in this section attempt to develop an efficient coherence mechanism by supporting snooping over point to point networks. In the full map directory scheme [11], each node maintains a directory of all the memory blocks mapped onto that node. In this scheme, the directory entry for a block consists of the state of the block and a presence bit vector indicating the caches with a copy of the block. Although the full map directory scheme performs well [6] ....

L. M. Censier and P. Feautrier, "A new solution to coherence problems in multicache systems," IEEE Trans. Comput., vol. C-27, no. 12, pp. 1112--1118, Dec. 1978.

....(MC) and a network interface. The nodes are connected to a router through the network interface via internal links. The input and output links of a router connect to other routers to form the torus network structure. The system implements a full map directory based cache coherence scheme [15] which will be described later. The processors are assumed to have only a single thread and no prefetching of cache blocks is performed. The system is assumed to be sequentially consistent, which means that there are no write buffers and cache misses on load or store operations block the ....

....link is routed on odd channels if the ith digit of the destination node is greater than the ith digit of the current node, otherwise, the message is routed on even channels. 2. 2 Cache coherence protocol and synchronization We implemented the full map directory based cache coherence protocol [15] for evaluation in this paper. In this scheme, each shared memory block is assigned to a node, called home node, which maintains the directory entries for that block. Each entry in the directory is a bitvector of same length as the number of nodes. The directory also maintains the information ....

L. M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Transactions on Computers, vol. C-27, no. 12, pp. 1112--1118, December 1978.

....and writable copies of each memory line for multiprocessors. Modification of one copy of a datum may require updating of other copies to maintain consistency among them. Several coherence protocols have been proposed for distributed multiprocessor architectures but few are formally verified [1, 15, 2, 10]. This research was supported by the Advanced Research Projects Agency through NASA grant NAG 2 891. Formal verification is desirable because there could be subtle bugs as the complexity of protocols increases. Although finite state methods (e.g. 3, 5] can solve many verification problems ....

L. Censier and P. Feautrier. A new solution to coherence problems in multicache systems. IEEE Transactions on Computers, 27(12):1112--1118, December 1978.

....Architectural Assumptions We will consider a multiprocessor architecture consisting of processor nodes connected by an interconnection network. Each processing node contains a processor, a processor cache, and a memory module. Data coherence is maintained in hardware using a directory protocol [4]. There are four levels in the memory hierarchy. The first level consists of the local processor caches. Local memory is the second level. The third level includes the caches of all other nodes. The fourth level consists of all nonlocal memory modules. Each memory module contains random access ....

L.M. Censier and P. Feautier. A new solution to coher- ence problems in multicache systems. IEEE Transactions on Computers, 27:1112-1118, December 1978.

....Architectural Assumptions We will consider a multiprocessor architecture consisting of processor nodes connected by an interconnection network. Each processing node contains a processor, a processor cache, and a memory module. Data coherence is maintained in hardware using a directory protocol [5]. There are four levels in the memory hierarchy. The first level consists of the local processor caches. Local memory is the second level. The third level includes the caches of all other nodes. The fourth level consists of all nonlocal memory modules. Each memory module contains random access ....

L.M. Censier and P. Feautier. A new solution to coherence problems in multicache systems. IEEE Transactions on Computers, 27:1112-1118, December 1978.

....with large numbers of processors that rely on snoopy cache strategies to maintain cache consistency have severe interconnect design constraints due to their reliance on broadcast messages. From the standpoint of interconnect design, a more versatile class of protocols is directory protocols [18, 3, 2, 1]. In these schemes a separate directory memory is maintained that identifies the caches containing each cache line sized block of memory. When data is written, the directory information is used to direct invalidation or update messages (depending on the type of protocol) to only those caches that ....

....networks, and are therefore an attractive option for large scale multiprocessors. Perhaps the most straightforward directory scheme that maintains full information in the directory about the current state of cached data is an invalidation protocol described by Censier and Feautrier [3]. The Dur ng the remainder of the paper we will discuss only inval idation protocols for brevity. Most coherence strategies proposed for large scale machines are invalidation based, and while the issue of updates vs. invalidates is an interesting one, it is orthogonal to the topic this paper ....

Lucien M. Censier and Paul Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers', C-27(12):1112-1118, De- cember 1978.

....memory consistency models and software controlled data prefetch are described, and their impact on the cache coherence protocols is examined. 2.1 Memory Consistency Models Memory consistency models describe the ordering of memory access events as seen by the programmer. Censier and Feautrier [12] define memory system coherence as follows Definition 2.1 A memory scheme is coherent if the value returned on a load instruction is always the value given by the latest store instruction with the same address. The problem with this definition is that the meaning of latest store is unclear. To ....

Lucien M. Censier and Paul Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, C-27(12):1112--1118, December 1978.

....out the similarity between cache coherence schemes and coherence control in transaction processing. The Liquid system used a bus based protocol similar to a snooping cache coherence protocol [21] SUDS uses a scalable protocol that is more similar to a directory based cache coherence protocol [9, 2, 1] with only a single pointer per entry, sometimes referred to as a Dir1B protocol. The ParaTran system for parallelizing mostly functional code [49] was another early proposal that relied on speculation. ParaTran was implemented in software on a shared memory multiprocessor. The protocols were ....

L. M. Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, C-27(12):1112--1118, Dec. 1978.

....protocol can significantly reduce the cache miss rate by up to 71 and the network traffic by up to 26 as compared to a write invalidate protocol. 3 The Scalable Tree Protocol An Alternative Directory Organization In the baseline protocol the directory is implemented with bit vectors [4]. One bit vector is associated with each memory block and each bit vector is N bits long, given that the system has N caches. Such a directory is called a full map directory. Unfortunately, the implementation cost of the directory becomes very high for large scale systems since the length of the ....

L.M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Transactions on Computers, C-27(12):1112-1118, December 1978.

....consists of a processor with its cache hierarchy, a memory module, a local bus, and a network interface connecting the processor node to the network as shown in Figure 1. Both the hardware only and the software only directory systems employ a write invalidate protocol with a full map directory [3]. A processor read that misses in the second level cache (SLC) initiates a read miss request to the home node, i.e, the node where the memory block is mapped. If the memory copy is clean, home responds with a block copy to the local requesting node and updates the directory. Otherwise, if another ....

L.M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Trans. on Computers, C27 (12):1112-1118, Dec. 1978.

....node consists of a processor with its cache hierarchy, a memory module, a local bus, and a network interface connecting the processor node to the network as shown in Fig. 1. The hardware only and the software only directory systems both employ a writeinvalidate protocol with a full map directory [4]; i.e. for each memory block a presence flag vector is used to indicate which nodes have a copy of the block. A processor read operation that misses in the second level cache (SLC) initiates a read miss request which is sent to the node where the memory block is mapped, denoted the home node. If ....

L. M. Censier and P. Feautrier, A new solution to coherence problems in multicache systems, IEEE Trans. Comput. C-27, 12 (December 1978), 1112#1118.

....protocols is to reduce memory system contention by exclusively sending point to point messages to those caches that share a copy of one memory block. This is achieved by associating the same number of cache pointers as the number of caches with each directory entry. In full map directory schemes [3, 8] the cache pointers are represented by a bit vector containing N bits, where N is the number of caches. Since one bit vector is associated with each memory block, the resulting implementation cost for the directory is unacceptable for multiprocessors containing several hundreds of caches. ....

L. M. Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, C-27(12):1112--1118, 1978.

....action. The protocol assumes two stable states for a memory block: clean and dirty. In addition, a number of transient states are used to indicate pending protocol transactions. Coherence requests to blocks in transient states have to be retried as in, e.g. DASH [16] A full map directory [4] keeps track of which caches having copies of a memory block and the protocol actions are as follows. Read misses in the SLC are sent to home. If the block is clean, home sends a block copy to local and updates the directory with the identity of local. Otherwise, if the block is dirty, home ....

L. M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Transaction on Computers, C-27(12):1112-1118, December 1978.

....NI Interconnection Network 4 To understand the effects latency tolerating and reducing techniques have on the execution time, a basic understanding of how the cache coherence protocol works is essential. The cache coherence protocol is a write invalidate protocol with a full map directory [4], i.e. for each memory block a presence flag vector is used to indicate which nodes having a copy of the block. When describing the coherence actions of the protocol we will refer to the nodes involved as follows; home is the node where the page containing the block is allocated, local is the ....

L.M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Transaction on Computers, C-27(12):1112-1118, December 1978.

....protocols. Instead, in this paper we focus on the performance and implementation tradeoffs of three protocols that maintain exact information about the sharing set but that differ considerably in hardware complexity full map, linear list, and tree based protocols. In full map directory schemes [4, 13] the cache pointers are represented by a bit vector containing N bits, where N is the number of caches. Since a bit vector is associated with each memory block, the resulting implementation cost for the directory is unacceptable for multiprocessors containing several hundreds of caches. For large ....

....outline the three protocols we experimentally evaluate in Section 4. We especially focus on the read and write latency differences associated with the protocol actions. In Section 2. 2 we describe a full map protocol based on the presence flag protocol originally proposed by Censier and Feautrier [4]. In Section 2.3 we present the linear list protocol, based on the IEEE P1596 standard (SCI) and in Section 2.4 we present our tree based protocol, the STP. 2.1 Framework for comparison To compare the protocols in a consistent manner we have made a set of basic assumptions regarding their ....

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L. M. Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, C-27(12):1112-- 1118, 1978.

....side effect of using multiple paths between a pair of nodes is that messages from a source may arrive at a destination in different orders. This is known as the pairwise out of order (OoO) message arrival problem. Although exceptions exist [17, 16] many directory based cache coherence protocols [27, 30, 4] designed for DSM systems require pairwise in order arrival to make the design and verification easier [28] To exploit the advantages of a multiple path network in a DSM system, architects currently use one of two alternative strategies. The first strategy, represented by SGI Origin, is to ....

....uniform network between a source destination pair in a system using the T FIFO strategy. between pairwise messages safely. This in order arrival property effectively prevents almost all difficult race conditions from occurring. Most existing cache coherence protocols can be used by this strategy [27, 30, 4, 5, 23, 22]. Since these coherence protocols are well understood, no further discussions are provided. 4.2 The Network Interface CC NUMA systems using the T FIFO strategy demand two basic functions from the network interface: a) to detect the occurrences of pairwise out of order (OoO) arrivals and (b) to ....

M. Censier and P. Feautier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, 27:1112--1118, December 1978.

....and the line size is 32 bytes. We use the simple software scheme [8] to maintain processor cache coherence in most of our experiments. We also use the directory scheme in one experiment. The directory scheme in this study is based on Censier and Feautrier s distributed full map directory scheme [2]. For the software scheme, we use a write through write allocate cache with a small write back cache as its write buffer [3] This write policy was shown to have better performance than pure write through or write back caches for software schemes. 20 30 40 50 60 70 80 90 100 0.5 1 2 4 8 ....

L.M. Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. Transactions on Computers, C-27:1112--1118, November 1978.

....scalable. For medium and large scale multiprocessors, a scalable interconnection network such as a mesh, or a torus, is needed [7] This could make snooping unsuitable to be implemented on such interconnects. Directory based protocols were first proposed by Tang [24] and Censier and Feautrier [3]. The basic idea is to keep a directory entry for every memory line. This entry consists of its state and a sharing code [16] indicating the caches that contain a copy of the line. Each coherence transaction is sent to a directory controller which, in turn, using its corresponding directory entry, ....

L.M. Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transaction on Computers, 27(12), pp. 1112-1118, December 1978.

....examine this behaviour, and try to quantify what happens when it is coupled with a recovery protocol. Chapter 2 Modelling 31 2. 1 SMP Cache Coherence Protocols 1 A cache system is said to be coherent if every read of a memory location returns the value most recently written to that location [Censier et al. 78] In a shared memory multiprocessor where processors access shared memory through private caches, there can be potentially as many copies of the same memory location as there are processors in the architecture. Inconsistencies may occur when several processors access writable shared data. When ....

CENSIER, L.M., AND FEAUTRIER, P. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, pp.1112--1118, Vol.27, No.12, December 1978.

.... variable, some coherence mechanism is required to ensure that when a processor reads a shared variable, it always receives the most current value [9] One type of coherence mechanism uses directories located in the shared memory to keep track of which processors have cached copies of which blocks [2 4]. The number of entries in these traditional directories is proportional to the size of the main memory because the bits used to point to the processors with cached copies of a block are associated with each block in the memory. Since the data caches are significantly smaller than the main memory, ....

L. M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Tran. Computers, C-27(12):1112-1118, Dec. 1978.

....consistent. Similarly, much of the work on cache algorithms focuses on cache coherence, a stronger property than sequential consistency. A memory scheme is coherent if the value returned on a LOAD instruction is always the value given by the latest STORE instruction with the same address [CF78] As noted by Scheurich and Dubois, this definition makes implicit architectural assumptions (specifically as to the atomicity of write operations) that limit its applicability to some multiprocessor architectures [SD87] For systems in which this definition has a natural interpretation, ....

L. M. Censier and P. Feautrier. A new solution to coherence problems in multicache systems. IEEE Transactions on Computers, C-27:1112--1118, 1978.

....fashion. In chapter 2, the problems related to bus based parallel computers will be discussed more thoroughly, together with some alternatives. 2 In the second half of the seventies, the use of directories to identify the caches sharing the same memory line was proposed by [Tang, 1976] and [Censier and Feautrier, 1978]. Instead of broadcasting update messages to all caches, they propose to send update messages to each individual cache identied by the directory. One distinguishes between a centralized directory, where a central directory identies the caches storing the same line, and a chained directory, where ....

....This standard describes a physical interconnect and a protocol, showing how a computer with multiple processors and distributed shared memory can be designed. The SCI standard describes a protocol which ensure cache coherence and this part is clearly based on the ideas proposed by [Tang, 1976] [Censier and Feautrier, 1978] and [Chaiken et.al. 1990] because the SCI cache coherence protocol uses a distributed directory to identify the sharing caches. One of the goals when SCI was developed, was to ensure scalability so that the performance increases when the number of processors and memory chips increase. In ....

[Article contains additional citation context not shown here]

Lucien M.Censier, Paul Feautrier. 'A New Solution to Coherence Problems in Multicache Systems IEEE Transactions on Computers, Vol.27, No.12, December 1978, p.1112-1118 153

....a copy of the line. The choice of interconnect may influence the design of the cache coherency protocol. For example, if the network supports efficient broadcast operations, then a snoopy cache coherence protocol (e.g. McCreight 84] can be used. Otherwise, directory based protocols (such as [Censier Feautrier 78] are more attractive. However, the difference 2 The Cray T3D uses an approach similar in spirit. However, the T3D is supposed to scale to large numbers of nodes, and sacrificing enough high order physical address bits to encode that many processing node numbers would reduce the available ....

L. M. Censier and P. Feautrier. A new solution to coherence problems in multicache systems. IEEE Transactions on Computers, pages 1112-- 1118, December 1978.

....two separate phases allows an even greater overlap of memory operations by all processors. 8.1. 2 Coherence Mechanisms The coherence mechanisms that implement these memory consistency models fall into two general categories: snooping schemes [Arc86,Goo83,Kat85,Tha87] and directory based schemes [Aga88,Cen78,Cha91,Len90,OKr90]. The best solution for a given system Chapter 8: Other Systems Issues 159 depends on several factors, including the number of processors, the anticipated workloads, the desired memory consistency model, and the desired system cost. 8.1.2.1 Snooping As noted in Section 7.6, snooping coherence ....

....more flexibility in the choice of memory model presented to the programmer. Directory based approaches require a processor to communicate with a common directory whenever the CPU s actions may cause an inconsistency between its local memory and those of other processors or the global shared memory [Cen78]. The directory maintains information about which processors have a copy of which objects. Before a processor can write to an object, it must request exclusive access from the directory. The directory sends messages to all processors with a local copy of the object, forcing them to invalidate ....

L.M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems", IEEE Transactions on Computers, C-27(12):11121118, December 1978. Cited in [Lil93].

....the risk of reading an old copy. A cache coherence protocol is needed to ensure that the shared address space is kept coherent at all times. A memory is considered coherent if the value returned by a read from a location of the shared address space is the value of the latest store to that location [7]. Cache coherence protocol can be divided into two categories. The first one assumes that there is only one copy of a page with write access mode and all other copies are in read only access mode. The processor that has the page in write access mode is called the owner of the page. When a ....

L.M. Censier and P. Feautrier. A new solution to coherence problems in multicache systems. IEEE Trans. on Computers., C-27(12):1112--1118, Dec 1978.

....the risk of reading an old copy. A cache coherence protocol is needed to ensure that the shared address space is kept coherent at all times. A memory is considered coherent if the value returned by a read from a location of the shared address space is the value of the latest store to that location [1]. A solution is to have either only one copy of a page with write access mode or multiple copies in read only access mode. The processor that has written most recently into the page is called the owner of the page. When a processor needs to write to a page that is not present in its cache or is ....

L.M. Censier and P. Feautrier. A new solution to coherence problems in multicache systems. IEEE Trans. on Computers., C-27(12):1112--1118, Dec 1978.

....that scale the unit of sharing to a virtual memory page in order to increase performance. Another option for improving performance is to define less restrictive definitions of memory consistency than the standard (strong consistency) criterion, stating that reads return the most recent write [2]. Propositions for relaxed definitions of memory consistency include weak consistency [3] release consistency [4] and entry consistency [5] Studies on sharing and synchronization in parallel programs (e.g. 6] showed that each consistency protocol is better suited to a different class of ....

L. M. Censier and P. Feautrier. A new solution to coherence problems in multicache systems. IEEE Transactions on Computers, 27(12):1112--1118, December 1978. 7

....global directory Another possible coherence mechanism is to keep track of all shared copies of a line in a global directory. The directory can be distributed along with the memory of the system (as opposed to a centralized directory as proposed by Tang[Tang76] Censier and Feautrier [Cens78] proposed keeping a bit vector of size N for each line, with the corresponding bit set for every processor that has a copy of the line. When the line is invalidated, individual messages are sent to each processor whose bit is set. This does not violate the bandwidth requirement for scalability, ....

....a mechanism for hierarchical read combining in a k ary n cube, based upon the read combining in multis. The hierarchical nature of pruning cache directories makes them compatible with this read combining mechanism. 1. Survey of Cache Coherence Mechanisms Recall that a full width global directory [Cens78] includes an N bit vector along with each line of main memory. As discussed in Chapter 2, the full width directory does not scale in cost, as it requires O (N 2 ) directory space (assuming a total memory size that grows linearly with the number of processors) There have been many proposals for ....

Censier, L. M. and P. Feautrier, A New Solution to Coherence Problems in Multicache Systems, IEEE Transactions on Computers C-27(12), December 1978, 1112-1118.

....by mesh networks that were separated for the request and reply. This structure provides both the simplicity of the SMP (implementation and programming model) within a cluster and the scalability for the inter cluster communication. DASH incorporated the directory based cache coherence mechanism [8], which is considered to be more scalable than the snooping scheme. DASH s cluster organization was beneficial when combined with the directory based cache coherence mechanism: each bit in a directory entry represents a cluster not a processor. Therefore, the memory overhead for directory entries ....

....are snooped by each processing element to see if the PE has the requested data item. To give the cache controller enough time for this snooping operation, the processing of the request messages is pipelined. For medium to large scale multiprocessors, directory based coherence protocols are used [8]. On a directory based coherence protocol, associated with each memory block is a directory entry that keeps track of cached copies of the memory block. Full bitmap is a standard and popularly adopted structure for directory entries [40] In this scheme, each set bit represents a cache having a ....

L. M. Censier and P. Feautier, "A New Solution to Coherence Problems in Multicache Systems," Transactions on Computers, IEEE, Vol. c-27, No. 12, 1112--1118, December 1978.

....section, the small scale bus based multiprocessors rely on snoopy cache coherence mechanisms, which inherently use broadcast. Such schemes were not, however, the first protocols developed for cache coherence. Before the snoopy schemes were developed, directory based protocols had been proposed [CF78]. Directory based schemes rely on an extra structure called the directory that tracks which processors have cached any given block in main memory. The initial directory schemes assumed a single, monolithic directory, and we explain the basic operation of directory coherence using this assumption. ....

L. Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, C(27):1112-1118, December 1978.

....(ii) each node needs information about what local data are cached remotely to avoid superfluous transfers. In contrast to the request response DIVA where caching can be implemented with just a snoopy bus protocol [7] push mode DIVA requires an elaborate directory based cache coherence protocol [4] that can track the cached copies. For completeness we describe such a protocol in Appendix I. 3 DIVA and Data Optimization In a DIVA system, we distribute memory vectors across the nodes to maximize the available parallelism. Additionally, we want to align memory vectors accessed in the same ....

Lucien M. Censier and Paul Feautrier, "A New Solution to Coherence Problems in Multicache Systems." IEEE Transactions on Computers, Vol. 27, No. 12, pp. 1112-1118, December 1978.

....to performance [25] Our work uses prediction to reduce access latency in distributed shared memory systems by attempting to move data from their creation place to their use points as early as possible. In a distributed shared memory system, a coherence protocol typically directory based [5] (e.g. DASH [18] SCI [12] DIR i NB [1] etc. keeps processor caches coherent and transfers data among the nodes. In essence, the coherence protocol carries out all communication in the system. Coherence protocols can either invalidate or update shared copies of a data block whenever the data ....

L.M. Censier and P. Feautrier, "A New Solution to Coherence Problems in Multicache Systems." IEEE Trans. Computers, 27(12):1112-1118, Dec. 1978.

....memory contention in the entire system. However, in designing a shared memory SMP system where each processor is equipped with a cache memory, it is necessary to maintain coherence among the caches such that any memory access is guaranteed to return the latest version of the data in the system [Censier and Feautrier, 1978]. Cache coherence can be enforced through a shared snooping bus [Goodman, 1983, Sweazey and Smith, 1986] The basic idea is to rely on the broadcast nature of the bus to keep all the cache controllers informed of each other s activities so that they can perform the necessary operations to ....

Censier, L., and Feautrier, P. 1978. A New Solution to Coherence Problems in Multicache Systems. IEEE Trans. on Computers. C-27(12):1112--1118. 35

....at every point during program execution. Especially, a correct decision can be made whether an access to the cache is a hit or a miss. Furthermore, write serialization (important for coherence) can be enforced on the level of memory blocks. For more details on directory implementations, consult [2, 13] or [10] We differentiate between the two classes of invalidation and write update coherence protocols because these are distinct designs which exhibit strongly different performance behaviour. Invalidation protocols (INV) ensure that a processor has exclusive access to a data item before it ....

Lucien M. Censier and Paul Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, C-27(12):1112--1118, December 1978.

....coalescing write buffer before they can be issued to the L2 cache. If a read hits in either buffer, its result is forwarded to the processor and the cache line is not brought into the L1 cache. 2.3. 2 Directory Coherence Protocol We use a three state, fully mapped directory coherence protocol [CF78] The three states at the directory are: uncached, shared, or dirty. A cache line is in uncached state if it is not cached by any processor and memory contains the updated copy of the line. A line in shared state may be cached by one or more processors and the 12 directory contains the unmodified ....

Lucien M. Censier and Paul Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Trans. on Computers, C27 (12):1112--1118, December 1978.

....shared blocks to private blocks when a processor is about to write a location, then converts private blocks to shared blocks when another processor attempts to read a location previously marked as private. 1.2.2.2. The Presence Bit solution The Presence Bit solution for multicache coherence [44] is similar to Tang s solution. Instead of duplicating each cache s directory in a central directory, main memory has N 1 extra bits per block. N of these bits correspond to the caches in the system, and are set if and only if the corresponding cache has a copy of the block. The remaining bit is ....

Lucien M. Censier and Paul Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers C-27(12):1112-1118, December, 1978.

No context found.

L.M Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEEE Transactions on Computers, C-27(10):866--872, December 1978.

No context found.

L. M. Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, C-27(12):1112--1118, December 1978.

No context found.

L. Censier, P. Feautrier, "A New Solution to Coherence Problem in Multicache Systems," IEEE Transactions on Computers, C-27(12):1112-1118, December 1978.

No context found.

Lucien M. Censier and Paul Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, 27(12):1112--1118, December 1978.

No context found.

Censier, L.M. and Feautrier, P., "A new solution to coherence problems in multicache systems ", IEEE Trans. on Computers, Vol. C-27, No. 12, Dec. 1978, pp. 1112-1118.

No context found.

L. Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, C-27(12):1112-1118, December 1978.

No context found.

Censier, L.M. and P. Feautrier, P, "A new solution to coherence problems in multicache systems," IEEE Transactions on Computers, 27(12):1112-1118, December 1978.

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