A. Goel and W. R. Lee. Formal verification of an IBM CoreConnect processor local bus arbiter core. In Procs. of the 37th Design Automation Conference, pages 196-- 200, 2000. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
RTL Formal Verification of Embedded Processors - Bavonparadon, Chongstitvatana (2002) (Correct)
....processor verification do not verify a whole processor but they verify only some parts [6,9,11] This is because the size of the whole processor in full details is too large to be verifiable. Other approaches are model based approaches. These approaches are often used to verify control circuits [12,13,14], protocols [15] and asynchronous control circuits [16] Although there is an application of these approaches for verifying processors [17] but it is the verification at behavior level. There are only a few research that apply model based approaches to verify processors and there are only few ....
A. Goel, and W. R. Lee, "Formal Verification of an IBM CoreConnect Processor Local Bus Arbiter Core", Proceedings of the 37th Conference on Design Automation Conference (DAC'2000.
A Theory of Consistency for Modular Synchronous Systems - Bryant, Chauhan, Clarke, Goel (2000) (2 citations) (Correct)
....of its specification. In model checking [6] for example, a model of the design is verified against a set of tem poral logic properties. However, specifications might have errors themselves. The authors have discovered errors in protocol specifications for the PCI bus and the CoreConnect bus [4, 9]. This highlights the need to examine specifications more carefully. These problems often occur due to the limitations of natural languages used to describe specifications. However, even formal specifications can have problems. Sometimes, it is not possible to realize the specification in any ....
....to [6] 3 Synchronous Consistency Model The model we are proposing augments the state transition graph of the system with extra information to capture combinational dependencies. As discussed in the introduction, these dependencies are an important aspect of many bus protocol specifications [9]. Definition 1 (Synchronous Consistency Model (SCM) A synchronous consistency model M is a six tuple (5 , P, q) where 1. 5 is the set of observable states. 2. C 5 x 5 is a transition relation. 3. P is the set of micro states. 4. C: 5 P maps observable states to micro states. 5. ....
A. God, W. R. Lee. "Formal Verification of an IBM CoreConnect Processor Local Bus Arbiter Core." 37th AUM/IEEE Design Automation Uonfercncc. 2000.
A Theory of Consistency for Modular Synchronous Systems - Bryant, Chauhan, Clarke, Goel (2000) (2 citations) Self-citation (Goel) (Correct)
....terms of its specification. In model checking [6] for example, a model of the design is verified against a set of temporal logic properties. However, specifications might have errors themselves. The authors have discovered errors in protocol specifications for the PCI bus and the CoreConnect bus [4, 9]. This highlights the need to examine specifications more carefully. These problems often occur due to the limitations of natural languages used to describe specifications. However, even formal specifications can have problems. Sometimes, it is not possible to realize the specification in any ....
....to [6] 3 Synchronous Consistency Model The model we are proposing augments the state transition graph of the system with extra information to capture combinational dependencies. As discussed in the introduction, these dependencies are an important aspect of many bus protocol specifications [9]. Definition 1 (Synchronous Consistency Model (SCM) A synchronous consistency model M is a six tuple (S; R; P; C; n; Phi) where 1. S is the set of observable states. 2. R S Theta S is a transition relation. 3. P is the set of micro states. 4. C : S P maps observable states to ....
A. Goel, W. R. Lee. "Formal Verification of an IBM CoreConnect Processor Local Bus Arbiter Core." 37th ACM/IEEE Design Automation Conference. 2000.
Modeling Hardware Systems with Complex Clock.. - Sgm Formal Verifier (Correct)
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A. Goel and W. R. Lee. Formal verification of an IBM CoreConnect processor local bus arbiter core. In Procs. of the 37th Design Automation Conference, pages 196-- 200, 2000.
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