Browne M. C., Clarke E. M. and Dill D. [1985], Checking the correctness of sequential circuits, in `Proc. 1985 Int. IEEE Conf. on Computer Design', IEEE, Port Chester, New York. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Detecting Races in Relay Ladder Logic Programs - Aiken, Fähndrich, Su (1998) (12 citations) (Correct)
....once and then used repeatedly on different input configurations. Model Checking Model checking [12,13] is a branch of formal verification that can be fully automated. Model checking has been used successfully for verifying finite state systems such as hardware and communication protocols [7,8,14,15,20]. Model checkers exploit the finite nature of these systems by performing exhaustive state space searches. Because even these finite state spaces may be huge, model checking is usually applied to some abstract models of the actual system. These abstract systems are symbolically executed to obtain ....
M. Browne, E.M. Clarke, and D. Dill. Checking the correctness of sequential circuits. In Proc. IEEE Internat. Conf. on Computer Design, pages 545--548, 1985.
Detecting Races in Relay Ladder Logic Programs - Aiken, Fähndrich, Su (1998) (12 citations) (Correct)
....once and then used repeatedly on different input configurations. Model Checking Model checking [9, 10] is a branch of formal verification that can be fully automated. Model checking has been used successfully for verifying finite state systems such as hardware and communication protocols [6, 7, 12,17, 11]. Model checkers exploit the finite nature of these systems by performing exhaustive state space searches. Because even these finite state spaces may be huge, model checking is usually applied to some abstract models of the actual system. These abstract systems are symbolically executed to obtain ....
M. Browne, E.M. Clarke, and D. Dill. Checking the correctness of sequential circuits. In Proc. IEEE Internat. Conf. on Computer Design, pages 545--548, 1985.
Automatic Analysis of Relay Ladder Logic Programs - Su (1997) (Correct)
....because we work with an initially simplified constraint system. Model Checking Model checking [10, 11] is a branch of formal verification that can be fully automated. Model checking has been used successfully for verifying finite state systems such as hardware and communication protocols [7, 8, 13, 18, 12]. Model checkers exploit the finite nature of these systems by performing exhaustive state space searches. Because even these finite state spaces may be huge, model checking is usually applied to some abstract models of the actual system. Our analyses for RLL programs use similar techniques. ....
M. Browne, E.M. Clarke, and D. Dill. Checking the correctness of sequential circuits. In Proc. IEEE Internat. Conf. on Computer Design, pages 545--548, 1985.
Tableau-Based Model Checking in the Propositional Mu-Calculus - Cleaveland (1990) (62 citations) (Correct)
....properties of a system and a decision procedure to determine automatically if the start state of the system in question satisfies these formulas. Various temporal and modal logics have been investigated, and several case studies have pointed to the practical benefits of this form of verification [3, 4, 5]. One particularly expressive logic is the propositional mu calculus [16] A wide variety of branching time logics [12, 17, 21] including dynamic logic [14] and many temporal logics, have uniform encodings in this logic, and it also may be used to characterize fully the behavior of finite state ....
Browne, M.C., E.M. Clarke and D. Dill. "Checking the Correctness of Sequential Circuits. " In Proceedings of the 1985 IEEE International Conference on Computer Design, pp. 545-548.
Model Checking - Clarke, Schlingloff (2000) (755 citations) Self-citation (Clarke) (Correct)
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Browne M. C., Clarke E. M. and Dill D. [1985], Checking the correctness of sequential circuits, in `Proc. 1985 Int. IEEE Conf. on Computer Design', IEEE, Port Chester, New York.
Verification Tools for Finite-State Concurrent Systems - Clarke, Grumberg, Long (1993) (99 citations) Self-citation (Clarke) (Correct)
....problem for a variety of other temporal logics and showed, in particular, that for linear temporal logic the problem was PSPACE complete. A number of papers demonstrated how the temporal logic model checking procedure could be used for verifying network protocols and sequential circuits ( 10] [11], 12] 13] 27] 38] 63] In the case of sequential circuits two approaches were used for obtaining state transition graphs to analyze. The first approach extracted a state graph directly from the circuit under an appropriate timing model of circuit behavior. The second approach obtained a ....
M. C. Browne, E. M. Clarke, and D. Dill. Checking the correctness of sequential circuits. In Proceedings of the 1985 International Conference on Computer Design, Port Chester, New York, October 1985. IEEE.
Model Checking: Historical Perspective - And Example Extended (Correct)
No context found.
M. C. Browne, E. M. Clarke, and D. Dill. Checking the correctness of sequential circuits. In Proceedings of the 1985 International Conference on Computer Design, Port Chester, New York, October 1985. IEEE.
Automatic Analysis of Relay Ladder Logic Programs - Zhendong Su Eecs (1997) (Correct)
No context found.
M. Browne, E.M. Clarke, and D. Dill. Checking the correctness of sequential circuits. In Proc. IEEE Internat. Conf. on Computer Design, pages 545--548, 1985.
Enhancing Model Checking in Verification by AI Techniques - Buccafurri, Eiter.. (1999) (2 citations) (Correct)
No context found.
Browne, M.C., Clarke E. M., Dill, D., Checking the Correctness of Sequential Circuits. In Proc. 1985.
Automated Temporal Reasoning about Reactive Systems - Emerson (1996) (38 citations) (Correct)
No context found.
Browne, M., Clarke, E. M., and Dill, D. Checking the Correctness of sequential Circuits, Proc. 1985 IEEE Int.. Conf. Comput. Design, Port Chester, NY pp. 545-548
Model Checking and the Mu-calculus - Emerson (1997) (10 citations) (Correct)
No context found.
Browne, M., Clarke, E. M., and Dill, D. Checking the Correctness of sequential Circuits, Proc. 1985 IEEE Int.. Conf. Comput. Design, Port Chester, NY pp. 545-548
Enhancing Symbolic Model Checking by AI Techniques - Buccafurri, Eiter, Gottlob.. (1997) (3 citations) (Correct)
No context found.
Browne, M.C., Clarke E. M., Dill, D., Checking the Correctness of Sequential Circuits. In Proc. 1985 International Conference on Computer Design, Port Chester, New York, October 1985, IEEE.
Descriptive Complexity and Finite Models - Immerman, Kolaitis, (Eds.) (Correct)
No context found.
Browne, M., Clarke, E. M., and Dill, D. Checking the Correctness of sequential Circuits, Proc. 1985 IEEE Int.. Conf. Comput. Design, Port Chester, NY pp. 545-548
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