B.K. Mathew, S.A. McKee, J.B. Carter and A. Davis, "Algorithmic Foundations for a Parallel Vector Access Memory System". Manuscript, 2000. Home/Search Document Details and Download
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Strongly Competitive Algorithms for Caching with.. - Gaysinsky, Itai.. (Correct)
.... of the CLPP Main memory controllers The traditional use of hierarchical memory systems, consisting of several cache levels, helps to overcome the mismatch between CPU and memory speeds only to a limited extent [10] A significant reduction in memory latency is achieved by the RDRAM memory system [20]; RDRAM combines the usage of caching with the extended ability to accept new data requests while supplying previously referenced data. The memory throughput is the number of data requests that can be handled in parallel. Suppose that the CPU cache size is k and the RDRAM throughput is d, then the ....
B.K. Mathew, S.A. McKee, J.B. Carter and A. Davis, "Algorithmic Foundations for a Parallel Vector Access Memory System". Manuscript, 2000.
Research Statement - McKee Self-citation (Mckee) (Correct)
....faculty at Utah in summer, 1998, and have been involved in all aspects of the Impulse project, from the design and analysis of new remapping optimizations to the hardware build effort. In particular, my contributions include designing a subcomponent to access vector elements in parallel [HPCA 00, SPAA 00] guiding the development of analytic models to perform cost benefit analyses of applying each optimization; working closely with six graduate students to design and evaluate Impulse enabled memory optimizations [PACT 99, ISCA Memory Wall Workshop 00, HPCA 01] and to study the applicability of ....
B.K. Mathew, S.A. McKee, J.B. Carter, A. Davis, "Algorithmic Foundations for a Parallel Vector Access Memory System", Proc. 12th ACM Symposium on Parallel Algorithms and Architectures, July 2000.
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