L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM J. Comput., 13(2):409--422, May 1984.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... (Hartmanis Simon [10] iii) PLRAM s (Fortune Wyllie [8] iv) k PRAM s (Savitch Stimson [17] v) alternating Turing machines (Chandra, Kozen Stockmeyer [2] vi) LPRAM S (Savitch [16] vii) Concurrent Read Exclusive Write PRAM s (CREW PRAM s, see e.g. Stockmeyer Vishkin [19]) viii) SIMDAG s (Goldschlager [9] For definitions we refer to the open literature See Cook [4] for an excellent account of the current research on parallelism using circuit based models. As pointed out by van Emde Boas [22] there are various computa L tional correspondences between the ....

....for the practicality of the second machine class , as APM s capture the salient features of existing vector com i puters. Note that SIMDAG s are more or less identical to CRCWPRAM s ( concurrent rea d concurrent write parallel random access machines ) and the results of Stockmeyer Vishkin [19] can be brought to bear on APM s. We will briefly discuss the relation between APM s and circuits later in this section. In all results the logarithmic cost criterion will be assumed. A SIMDAG (Goldschlager [9] consists of a CPU, a set of parallel processing units (PPU 0, PPU1, with local ....

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Stockmeyer, L.J., and U. Vishkin, Simulation of parallel random access machines by circuits, SIAM J. Comput. 13(1984) 409'422.

.... parallel programming models form quite a menagerie: ffl Semaphores, CCRs, Monitors [BA90, AS83] ffl CSP, Occam [Hoa85] 17 ffl Data Flow model [AA82] ffl RPCs, Client Server models [BN84, MW91] ffl Petri Nets [Rei85] ffl Alternating Turing Machines [CKS81, Ruz80] ffl Boolean circuits [CSV84, SV84] ffl Systolic Arrays [Kun82] ffl Associative Processors [Pot92, SKA92] ffl PRAM (several varieties: EREW, CREW, several kinds of CRCW) FW78, Gol82, SS79] ffl V RAM (data parallel) model [Ble90, HS86] Each model sprang from a different research community in response to completely ....

.... parallel programming models form quite a menagerie: ffl Semaphores, CCRs, Monitors [BA90, AS83] ffl CSP, Occam [Hoa85] 17 ffl Data Flow model [AA82] ffl RPCs, Client Server models [BN84, MW91] ffl Petri Nets [Rei85] ffl Alternating Turing Machines [CKS81, Ruz80] ffl Boolean circuits [CSV84, SV84] ffl Systolic Arrays [Kun82] ffl Associative Processors [Pot92, SKA92] ffl PRAM (several varieties: EREW, CREW, several kinds of CRCW) FW78, Gol82, SS79] ffl V RAM (data parallel) model [Ble90, HS86] Each model sprang from a different research community in response to completely different ....

L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal of Computing, 13:409--422, 1984.

....cell will contain the value written by the processor of lowest index. In the read phase each processor may read from a cell; simultaneous reads from the same cell are permitted. We remark that this is the strongest model among the commonly used PRAM models ( 4] 13] 7] 10] It is shown in [5] that if the instruction set of a processor is restricted and the size of the shared memory is bounded by a polynomial in n then PRIORITY PRAMs and unbounded fan in Boolean circuits are time depth equivalent (allowing a polynomial blowup in the number of processors or gates) Thus the circuit ....

....[1] there exists a PRAM with a polynomial number of processors, which solves the PARITY in constant time. The proof shows the existence of that PRAM using probabilistic methods. In fact, in [1] the existence of a Boolean circuit is demonstrated, but this implies the existence of the PRAM by [5]) Thus intuitively a large machine can solve a small problem very fast when all of its processors are working on it. But how fast can it compute the PARITY of q bits if only q of its processors are allowed to work In order to be more precise, we define SACK OF PROCESSORS S(n; q) S(n; q) is ....

Stockmeyer, L., Vishkin, U.: Simulation of Parallel Random Access Machines by Circuits, SIAM J. Comput. vol 14, No. 3. pp. 688-708

....or local memory location, execute a single RAM instruction, and write into one global or local memory location. In CRCW PRAM simultaneous write are allowed, and write conflicts are solved assuming that all processors writing into the same location must write the same value (the COMMON model) In [SV84] it was proved that CRCW PRAM are equivalent to unbounded fan in circuits. 3 Weighted recognition trees In order to better understanding how the algorithm we will propose works and for introducing the notion of weighted recognition tree, we briefly present a strategy for recognizing ....

L. Stockmeyer and U. Vishkin, "Simulation of parallel random access machines by circuits," SIAM J 13: 409--422, 1984.

....proved yet. 9 1.3.2 Subclasses of L Boolean circuits are sometime referred to as a parallel model of computation. This comes from results relating the depth in Boolean circuits to the time in models of computation such as alternating Turing machines [20, 63] and parallel random access machines [74]. The fact is that bounded depth Boolean circuits appear to be very useful for characterizing subclasses of L. We define NC 1 as the set of languages recognized by a family of bounded fan in logarithmic depth polynomial size Boolean circuits. The class AC 0 is defined as the class of ....

L.J. Stockmeyer and U. Vishkin, Simulation of parallel random access machines by circuits, SIAM J. Compt. Vol.13 (2), 1984.

....and global memory cells; this will also be sufficient for our algorithms. Finally, we aim at simple programs for each processor. There seems to be no general agreement on what exactly this should mean, and we do not attempt to formalize this criterion; for a possible approach see for example [31]. Nonetheless, we feel that the PRAM algorithms presented in this paper fulfill this condition for any reasonable definition of simple program . The fundamental example of a feasible, time optimal CREW algorithm is the method for computing OR n in (n) steps mentioned above [9] which even works ....

L. Stockmeyer and U. Vishkin, Simulation of parallel random access machines by circuits, SIAM J. Comput. 13 (1984), 402--422.

....length of the longest directed path from an input to an output and its size is the number of edges in the graph. Since COMMON can compute the AND or OR of n bits in one step using n processors and one shared memory cell, it can easily simulate any unbounded fan in Boolean circuit. THEOREM 21.10 [SV84] Any unbounded fan in Boolean circuit of depth d and size s can be simulated by COMMON in d steps using s processors and s shared memory cells. Any Boolean function f : f0; 1g n f0; 1g can be expressed by a formula of size O(n2 n ) in disjunctive or conjunctive normal form and thus can be ....

....an AND. One processor from the unique group whose AND is 1 writes the answer. Thus it is impossible to get nontrivial lower bounds on time for CRCW PRAMs without restricting the number of processors or shared memory cells. EXERCISE 21.15 21.3 Relationships Between PRAMs and Other Models 21 [CSV84] Prove that any Boolean function computed by a Boolean circuit of depth O(log log n) can be computed by an unbounded fan in circuit of depth two and n O(1) size. The complexity classes NC k and AC k consist of those Boolean functions that can be computed in O( log n) k ) depth and n ....

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L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 13:404-- 422, 1984.

....21, D 8000 Munchen 2 Abstract CRCW PRAMs can be characterized in terms of unbounded fan in circuits. We introduce the notion of SELECT gates. Combining this with the concept of an unambiguous circuit we are able to give a circuit equivalent of EREW PRAMs, thus answering an open question of [SV84]. Moreover, circuits with SELECT gates characterize CRCW , CREW , ERCW , and EREW PRAMs in a uniform manner. Introduction Parallel random access machines (PRAMs) and uniform circuit families are very important models in parallel complexity theory. Other important models are alternating Turing ....

....particular AC k , classes that are again characterizable by several parallel models including circuits and PRAMs. There are, however, different possibilities to define PRAMs. AC k was characterized by CRCW PRAMs, i.e. PRAMs that allow both simultaneous read and write access to memory cells [SV84]. On the other hand AC k is also characterized in terms of unbounded fan in circuits and alternation bounded alternating Turing machines. The most favorite PRAM models are CREW PRAMs (where concurrent writing is forbidden) and EREWPRAMs (where concurrent writing and reading is forbidden) GR89, ....

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L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 13(2):409--422, May 1984.

....which is iterated some number f(n) of times at the beginning of the formula to be used on inputs of size n. Immerman showed that the languages definable in this way are exactly those recognizable by a certain type of parallel random access machine in time O(f(n) It was already known (e.g. [SV84]) that these parallel time classes were equal to certain combinatorial complexity classes defined in terms of boolean circuits. In Section 4 we give an overview of combinatorial complexity theory, and describe the important notion of uniformity. Circuit complexity classes involve infinite families ....

L. Stockmeyer and U. Vishkin, "Simulation of parallel random access machines by circuits," SIAM J. Comput. 13:2 (1984), 409-422.

....In particular we exhibit circuit classes exactly characterizing polynomially time bounded unambiguous augmented push down automata. Introduction An important object in parallel complexity theory, the class NC , can be characterized in terms of Parallel Random Access Machines, see e.g. [3, 4, 9], Boolean Circuits [3, 10] Augmented Pushdown Automata [7, 6] and Alternating Turing Machines [1, 7] There are close connections between these concepts, see e.g. 3, 5] In [5] unambiguous circuits were considered in order to characterize CREW PRAMs and to further relate them with the NC ....

....multiple 0 input to AND gates of unbounded fan in) This idea in mind, we will use unambiguous versions of AC k and SAC k and additionally UnambRAC k as a subclass of UnambSAC k , in which even the OR gates of bounded fan in are vulnerable. In analogy to CRCW TIME (log n) AC 1 of [9], CREW TIME (log n) UnambAC 1 was shown in [5] This result works with strongly unambiguous circuits, since CREWalgorithms do not allow any multiple write accesses regardless of the influence of the written memory cell to the final result. In addition we will consider in the following the ....

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L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM J. Comput., 13(2):409--422, May 1984.

....Our bounds are of course also sufficient. The question whether a random oracle achieves this separation is still open. 2 1. 4 Relations to PRAMs The model of small depth circuits has relations to computation by parallel random access machines (PRAM) In particular, Stockmeyer and Vishkin [SV] proved that any function that can be computed on a slightly limited PRAM with a polynomial number of processors in time T can also be computed by polynomial size unbounded fanin circuits of depth O(T ) The limitations on the PRAM was a limitation of the instructionset to only contain relatively ....

Stockmeyer L.J and Vishkin U. "Simulation of Parallel Random Access Machines by Circuits", 18 SIAM J. on Computing, vol 13(2), 1984, pp. 404-422.

....is also called the owner of that memory cell. All three different models mentioned so far proved to describe reasonable and robust complexity classes. The class of languages recognized by CRCW and CREW PRAMs in logarithmic time can also be characterized in terms of uniform Boolean circuits [SV84, Lan90] and the language class recognized by CROW PRAMs in logarithmic time is exactly the class of languages reducible to deterministic context free languages in logarithmic space and there is also a characterization in terms of auxiliary pushdown automata [DR86, Sud78] It is only natural to apply ....

....In particular, we will prove that EREW PRAMs can be simulated by OREW PRAMs, while increasing the running time only by a constant factor. Similarly, ERCWPRAMs can be simulated by ORCW PRAMs. Owner Read PRAMs We use a definition of PRAMs similar to Stockmeyer and Vishkin s definition in [SV84]: Each PRAM has an unbounded global memory and infinitely many processors. Each processor has an unbounded local memory and an instruction counter. The program for each processor must be the same and may consist of finitely many instructions. The available instruction set contains add, subtract, ....

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L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 13(2):409--422, May 1984.

....a common CRCW PRAM with e processors and s shared memory cells in time d 1. The simulation is straightforward: the PRAM has a cell for each gate of the circuit and a processor for each edge and values are propagated from the input of the circuit towards its output node. Stockmeyer and Vishkin [SV84] showed a simulation of CRCW PRAMs by unbounded fan in circuits. Their result is somewhat unsatisfactory because, for their simulation, they have to severely restrict the instruction set of processors in CRCW PRAMs, disallowing even natural operations like multiplication. Theorem 5.6 (Stockmeyer ....

....of CRCW PRAMs by unbounded fan in circuits. Their result is somewhat unsatisfactory because, for their simulation, they have to severely restrict the instruction set of processors in CRCW PRAMs, disallowing even natural operations like multiplication. Theorem 5. 6 (Stockmeyer and Vishkin [SV84] A priority PRAM with p processors running in time T , where each processor has a limited instruction set and the input is given in n blocks of n bits each, can be simulated by an unbounded fan in circuit of depth O(T ) and size bounded by a polynomial in n; p, and T . Using the known lower ....

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Larry J. Stockmeyer and Uzi Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 13(2):409--422, May 1984.

....different settings, are easily shown to be equivalent. The equivalence of first order definability and uniform families of AC 0 is explained, for example, by Immerman [32] The equivalence of uniform families of AC 0 and CRCW PRAMs is demonstrated, for example, by Stockmeyer and Vishkin [41]. Though these three different setting are easily shown to be equivalent, the fact that the result of Ajtai is not stated in the PRAM model may explain the fact that his result has been ignored so far by the designers of PRAM algorithms. We think, therefore, that a direct implementation of Ajtai s ....

L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 14:409--422, 1984.

....machines that are implemented using circuit technology, or to parallel models that are equivalent to circuits with respect to the time resource. The fixed structure of circuits as opposed to the programmable nature of some other parallel models facilitates the proof of lower bounds as noted by [Stockmeyer and Vishkin, 1984]. A shortcoming of the circuit model is that it does not provide a very good measure of hardware. The size of the circuit provides an upper bound on the hardware size but intuitively this is a poor bound because a circuit is not allowed to reuse any of its gates. Width seems to provide a ....

....the close relationship between ATMs and uniform families of bounded fanin Boolean circuits. Theorem 4. 7 [Ruzzo, 1981] If S and T are computable in deterministic time O(T (n) then ATIME, SPACE(T (n) S(n) UDEPTH, SIZE(T (n) 2 O(S(n) The next theorem of Ruzzo and Tompa, see [Stockmeyer and Vishkin, 1984] for a proof) shows that ATMs with alternation considered as a resource are a good model of unbounded fanin, parallel computation (see Section 4.4.1) Theorem 4.8 If T (n) and S(n) are suitable functions then ATM ALT, SPACE(T (n) S(n) CRCW PRAM TIME, PROC (T (n) 2 O(S(n) 4.4 The ....

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Stockmeyer, L. J. and Vishkin, U. 1984. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 13(2):409--422.

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L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM J. Comput., 13:409--422, 1984.

No context found.

L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM J. Comput., 13(2):409--422, May 1984.

No context found.

L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 13(2):409--422, May 1984.

No context found.

L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 13(2):409--422, May 1984.

No context found.

Larry Stockmeyer and Uzi Vishkin. Simulation of Parallel Random Access Machines by Circuits. SIAM Journal on Computing, 13(2):409-- 422, May1984.

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Stockmeyer, L.J. and Vishkin, U. 1984. Simulation of parallel random access machines by circuits. SIAM J. Comput. 13(2):409--422.

No context found.

Larry Stockmeyer and Uzi Vishkin. Simulation of parallel random access machines by circuits. SIAM J. Comput., 13(2), 409--422, 1984.

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L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 13(2):409--422, May 1984.

No context found.

L. Stockmeyer and U. Vishkin. Simulation of parallel random access machines by circuits. SIAM Journal on Computing, 13(2):409--422, May 1984.

No context found.

L. Stockmeyer and U. Vishkin, "Simulation of parallel random access machines by circuits", SIAM J. Comput. 13 (1984) 409-422.

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