L. Benini and G. De Micheli, "Transformation and synthesis of FSM's for low power gated clock implementation," IEEE Trans. ComputerAided Design, vol. 15, pp. 630--643, June 1996. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Individual Flip-Flops with Gated Clocks for Low Power Datapaths - Tomas Lang Enric (1997) (6 citations) (Correct)
....portions of the system [4] 6] such as inhibiting the register load and or inhibiting the clock (gated clock) Inhibiting register load is proposed in [1] but this does not reduce the effective load on the clock. The use of gated clocks to reduce the activity of logic modules is described in [3] [5] 12] 13] Our proposal is at a finer level of granularity in which individual flip flops are activated deactivated according to their local behavior. Flip flop structures are proposed and models for energy consumption are developed, resulting in criteria to select the most appropriate ....
L. Benini and G. De Micheli, "Transformation and synthesis of FSM's for low-power gated-clock implementation," in Int. Symp. Low Power Design, Apr. 1995, pp. 21--26.
Glitch Power Minimization by Selective Gate Freezing - Benini, De Micheli, Macii, .. (2000) (2 citations) Self-citation (Benini De micheli) (Correct)
No context found.
L. Benini and G. De Micheli, "Transformation and synthesis of FSM's for low power gated clock implementation," IEEE Trans. ComputerAided Design, vol. 15, pp. 630--643, June 1996.
A Survey of Design Techniques for System-Level Dynamic .. - Benini, Bogliolo, De.. (2000) (32 citations) Self-citation (Benini De micheli) (Correct)
No context found.
L. Benini and G. De Micheli, "Transformation and synthesis of FSM's for low power gated clock implementation," IEEE Trans. ComputerAided Design, vol. 15, pp. 630--643, June 1996.
High-Level Power Modeling, Estimation, and Optimization - Macii, Pedram, Somenzi (1998) (22 citations) (Correct)
No context found.
L. Benini and G. De Micheli, "Transformation and synthesis of FSM's for low power gated clock implementation," IEEE Trans. ComputerAided Design, vol. 15, no. 6, pp. 630--643, 1996.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC