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K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, April 1996.

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Compiler Optimization of Value Communication for Thread-Level.. - Zhai (2005)   (Correct)

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K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, April 1996.


Optimistic Intra-Transaction Parallelism - On Chip Multiprocessors (2005)   (Correct)

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K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, April 1996.


Tolerating Dependences Between Large Speculative.. - Christopher Colohan..   (Correct)

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K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, April 1996.


Hardware Support for Thread-Level Speculation - Steffan (2003)   (Correct)

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K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, April 1996.


Improving Cache Locality for Thread-Level Speculation Systems - Fung (2005)   (Correct)

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K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, April 1996.


Balanced Multithreading: Increasing Throughput via a.. - Tune, Kumar, Tullsen, .. (2004)   (Correct)

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K. C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28--40, 1996.


Design and Applications of a Virtual Context Architecture - Oehmke, Binkert.. (2004)   (Correct)

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Kenneth C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28-- 40, April 1996.


Demand-Only Broadcast: Reducing Register File and Bypass Power - In Clustered Execution   (Correct)

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K. C. Yeager. The MIPS R10000 superscalar microprocessor. In Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture, pages 28-- 41, 1996.


Demand-Only Broadcast: Reducing Register File and Bypass Power.. - Brown, Patt (2004)   (Correct)

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K. C. Yeager. The MIPS R10000 superscalar microprocessor. In Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture, pages 28--41, 1996.


Coherence Decoupling: Making Use of Incoherence - Huh, Chang, Burger, al. (2004)   (1 citation)  (Correct)

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K. C. Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, 16(2):28--40, Apr. 1996.


In Proc. 11th International Parallel Processing.. - Silvia Mueller..   (Correct)

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K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28--40, 1996. 7


One-Cycle Zero-Offset Loads - Morancho, Llaberia, Olive, Jimenez (1998)   (Correct)

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K. C. Yeager, The MIPS R10000 SuperScalar Microprocessor. Microprocessor Report, 10 (14), 1996, 28-40


Precise Exceptions in Asynchronous Processors - Manohar, Nyström, Martin (2001)   (Correct)

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Ken Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, 16(2):28--40, April 1996.


Checkpoint Processing and Recovery: - Towards Scalable Large   (Correct)

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K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28--40, April 1996.


Next-Generation Memory Systems - Wang (2004)   (Correct)

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Kenneth C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28--40, April 1996.


Speculative Sequential Consistency with Little Custom Storage - Gniady, Falsafi (2003)   (Correct)

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Kenneth C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2), April 1996.


Dynamically Reducing Pressure on the Physical.. - Tran, Nelson.. (2004)   (Correct)

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K. Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, 6(2):28--40, April 1996.


Latency Tolerant Architectures - Bennett (1998)   (2 citations)  (Correct)

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K. Yeager. The Mips R10000 superscalar microprocessor. IEEE Micro, 16:28-- 41, April 1996.


Quantifying Instruction Criticality - Eric Tune Dean (2002)   (2 citations)  (Correct)

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K. C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28--40, 1996. 22


Improving Latency Tolerance of Multithreading through - Decoupling Joan-Manuel..   (Correct)

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K.C. Yaeger. The Mips R10000 Superscalar Microprocessor. IEEE Micro, April 1996, 16 (2) pp 2841.


Checkpoint Processing and Recovery: - Towards Scalable Large   (Correct)

No context found.

K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28--40, April 1996.


Hardware Support for Thread-Level Speculation - Steffan (2003)   (Correct)

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K. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, April 1996.


Physical Register Inlining - Lipasti, Mestan, Gunadi (2004)   (Correct)

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K. C. Yeager. Mips R10000 superscalar microprocessor. IEEE Micro, 1996.


Exploring Wakeup-Free Instruction Scheduling - Jie Hu Vijaykrishnan   (Correct)

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K. C. Yeager. The mips r10000 superscalar microprocessor. IEEE Micro, pages 28--40, 1996.


Implications of Register and Memory Temporal Locality.. - Morano, Khalafi.. (2002)   (Correct)

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Yeager K.C. The MIPS R10000 superscalar microprocessor. IEEE Micro, pages 28--40, Apr 1996.

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