R. Patton, The war on noise: new tools needed to attack the noise problem in deep-submicron design, Electron. J. (1998) 14}17.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....IC design processes, coupling e ects cannot be accurately estimated until the physical layout of a CMOS integrated circuit is determined. Therefore, several design iterations may be required to minimize the e ects of interconnect coupling capacitance to satisfy a target performance requirement [21,22]. In order to reduce both the design cost and time, coupling e ects should also be estimated at the system level [29] The coupling noise voltage on a quiet interconnect line has been analyzed by Shoji in Ref. 3] using a simple linear RC circuit. Delay uncertainty and noise expressions of coupled ....

R. Patton, The war on noise: new tools needed to attack the noise problem in deep-submicron design, Electron. J. (1998) 14}17.

....is reduced and or the aspect ratio of the interconnect thickness to width increases. The coupling capacitance may become comparable to the line to ground interconnect capacitance. Therefore, coupling has emerged as one of the primary issues in evaluating the signal integrity of VLSI circuits [5] [6]. The importance of interconnect coupling capacitances depends upon the behavior of the CMOS logic gates. If the logic gates driving the coupled interconnections are in transition, the coupling capacitance can affect the propagation delay and the waveform shape of the output voltage signal. If one ....

R. Patton, "The War on Noise: New Tools Needed to Attack the Noise Problem in Deep-Submicron Design," Electronics Journal, pp. 14--17, October 1998.

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