A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conference, pages 59--63, 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of (1) reduces to d(p) if fflp = in , i.e. if p is a source place of . Note that for Petri nets whose choices are either free choice or unique choice, the set of underlying structures resulting from all possible timed executions coincides with that from all possible untimed processes [HB95b, SY96] In the next section, we will take the advantage of this important fact to decouple the decisions from timing and consequently achieve bounds on the TSEs. For a given timed execution of Sigma, the time separation of event pair (s ) denoted by, fl (s; t; is the time distance ....

A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conference, pages 59--63, 1996.

....the time between the enabledness of the gate and the actual change at the output. The calculation of the language generated by a timed system is proven to be PSPACE complete [1] and demonstrated to be highly complex in several contexts such as real time systems [1, 15] and asynchronous circuits [13, 9, 16, 18, 24, 27]. Difference bounds matrices [5] and decision diagrams [8] have been used to efficiently represent timed polyhedra. Even though these techniques have been combined with partially ordered sets [7] the size of the untimed state space is still the major bottleneck for the analysis of highly ....

A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. Design Automation Conference, 1996.

....an unfolding of the system. Circuit synthesis is accomplished by approximating and refining covers for segments of the unfolding [9] However, adding time to unfolding greatly complicates the process yielding an explosion in the number of unfoldings required to capture all behaviors of the system [10]. In general, the addition of time to state space exploration exacerbates state explosion. Each state must include a set of possibly infinite timing configurations. Time can be divided into a minimum discrete quantum to limit the number of time configurations found at a single state [11] This ....

....where I # contains the relation xC xB # 0. However, if B and C are concurrent in the marking of the net, then it is possible to construct a zone I that does not include any explicit relations ordering the times of B and C, thereby creating a single equivalence class to cover all A C B D E [2,10] [2,5] 1,2] 6,10] 3,7] p 2 p 5 p 3 p 4 p 1 Figure 1. A fragment of a simple TPN. timed states at . This is the idea of the POSet al..gorithm in [23, 24] The POSet al..gorithm strives to never relate independent transitions in the net. However, because it still explicitly considers ....

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A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conf., pages 59--63, 1996.

....since each untimed state has at least one geometric region associated with it for every firing sequence that can result in that state. In highly concurrent systems where many interleavings are possible, the number of geometric regions per untimed state can be huge. Some researchers [10] [11], 12] 13] have attacked this problem by reducing the number of interleavings explored using the partial order techniques developed for untimed systems. These algorithms reduce verification time by exploring only part of the timed state space, but the improvement is dependent on the property to ....

....verification time by exploring only part of the timed state space, but the improvement is dependent on the property to be verified. The reduction in interleavings also prevents these techniques from being used for synthesis. Finally, even though the number of interleavings is reduced, in [10] [11] one region is still required for every firing sequence explored to reach a state. If most interleavings need to be explored, these techniques could still result in state explosion. The algorithm presented in [14] 15] 16] significantly reduces the number of regions per untimed state by using ....

Alexei Semenov and Alex Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conference, pages 59--63, 1996.

....the time between the enabledness of the gate and the actual change at the output. The calculation of the language generated by a timed system is proven to be PSPACE complete [1] and demonstrated to be highly complex in several contexts such as real time systems [1, 15] and asynchronous circuits [13, 9, 16, 18, 24, 27]. Difference bounds matrices [5] and decision diagrams [8] have been used to efficiently represent timed polyhedra. Even though these techniques have been combined with partially ordered sets [7] the size of the untimed state space is still the major bottleneck for the analysis of highly ....

A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. Design Automation Conference, 1996.

....the gate and the actual change at the output. The calculation of the language generated by a timed system has been proven to be PSPACEcomplete [AD90] and demonstrated to be highly complex in several contexts such as real time systems [AD90, HMP91] and asynchronous circuits [DKMW92, Bur92, HB94, SY96, VdJL96] Geometric regions combined with partially ordered sets have been recently used to verify highly concurrent systems [BM98] Although geometric regions can represent clock zones efficiently, they still suffer from the problem of dealing with a large number of untimed states. This paper ....

A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conference, 1996.

....given control circuit exhibits the specified behavior, and therefore is hazard free, is especially useful [54] In many practical circuits, the absence of hazards depends on assumptions on the relative delays of the various circuit elements. Examples of tools to check these timing assumptions are [55], 56] Synthesis of asynchronous control circuits is becoming a mature technology. Most computer aided design (CAD) tools synthesize these circuits from one of two specificiation styles: burst mode, a Mealy type state machine description [57] 58] 59] 52] and signal transition graphs, or ....

A. Semenov and A. Yakovlev, "Verification of asynchronous circuits using time petri net unfolding," in 33rd ACM/IEEE Design Automation Conference, June 1996.

....are not relevant to the property that is being verified. These approaches have been successful, but they only deal with untimed verification. The state space of timed systems is even larger than the state space of untimed systems and has been more difficult to reduce. Yoneda [73] Semenov [61], Verlind [71] and Bengtsson [11] have attacked this problem by reducing the number of interleavings explored using the partial order techniques developed for untimed systems. These algorithms compute a set of event firings that must be interleaved to ensure that the 8 desired property is ....

....compute a set of event firings that must be interleaved to ensure that the 8 desired property is checked. Any event firings not in the set are not interleaved. This reduces the state space significantly for highly concurrent specifications. While reducing the number of interleavings is useful, in [73, 61] one region is still required for every firing sequence explored to reach a state. If most interleavings need to be explored, these techniques could still result in state explosion. The algorithms from [71, 11] do address the problem of generating a unique region for every firing sequence. In [71] ....

Semenov, A., and Yakovlev, A. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conference (1996), pp. 59--63.

.... (s (j) d(p) reduces to d(p) if fflp = in , i.e. if p is a source place of . Note that for Petri nets with only free choice and unique choice, the set of underlying structures resulting from all possible timed executions coincides with that from all possible untimed processes [HB95b, SY96] This fact will be used later to decouple the decision from timing. For a given timed execution , the time separation of event pair (s (k) t (k ) denoted by, fl (k) s; t; is the time difference between their occurrences. That is, fl (k) s; t; t (k ) Gamma (s ....

A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petrinet unfolding. In Proc. ACM/IEEE Design Automation Conference, pages 59--63, 1996.

....term (s (j) d(p) reduces to d(p) if fflp = in , i.e. if p is a source place of . Note that for Petri nets with only free choice and unique choice, the set of event graph structures resulting from all possible timed executions coincides with that from all possible untimed processes [22, 32]. This fact will be exploited later to decouple the choice decisions from the timing behavior. 2.5 TSEs and their statistics Given a timed execution , the Time Separation of an Event pair (TSE) is the time distance between their occurrences. More precisely, the TSE of event pair (Invited ....

A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conference, pages 59--63, 1996.

....explored using the partial order techniques developed for untimed systems. These algorithms reduce verification time by exploring only part of the timed state space, but this may limit the timing properties that can be verified. While reducing the number of interleavings is useful, in [10, 11] one region is still required for every firing sequence explored to reach a state. If most interleavings need to be explored, these techniques could still result in state explosion. The algorithm presented in [13, 14] significantly reduces the number of regions per untimed state by using partially ....

A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conference, pages 59--63, 1996.

....regions for the analysis of synchronous programs like Esterel. Since these approaches builds the timed state graph they remain susceptible to the state explosion problem. Also, it may be necessary to associate a large number of timing regions to each (timed) state. Verlin et al. 40] and Semenov [37] try to alleviate the state explosion problem by using partial order techniques when constructing the timed state graph. Verlin extends Orbits while Semenov extends the work by McMillan [30] constructing a timed unfolding of the Petri net. These techniques have only been demonstrated on small ....

A. Semenov and A. Yakolev. Verification of asynchronous circuits using time Petri net unfolding. In International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 199--210, November 1995.

....term (s (j) d(p) reduces to d(p) if fflp = in , i.e. if p is a source place of . Note that for Petri nets with only free choice and unique choice, the set of underlying structures resulting from all possible timed executions coincides with that from all possible untimed processes [22, 32]. This fact will be used later to decouple the decision from timing. For a given timed execution , the time separation of event pair (s (k) t (k ) denoted by, fl (k) s; t; is t 1 (1) t 1 (2) t 3 (1) t 2 (1) t 4 (1) t 3 (2) p 3 p 1 p 2 p 1 p 1 p 2 p 2 p 4 p 3 p 3 2.5 0.4 ....

A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conference, pages 59--63, 1996.

....the logic circuits obtained through SIS and so on. Additionally, the designer may apply some last minute re orderings into the STG, especially when solving the Complete State Coding problem 2 . In the future we would like to add to these tools timing analysis software based on time Petri nets [35], to facilitate designs that are less conservative than purely speed independent circuits. 2 Unfortunately, none of the existing STG based software tools, including SIS, is capable of dealing with a sufficiently wide class of STGs as yet; the tool usually needs an active role played by the ....

A. Semenov and A. Yakovlev, "Verification of asynchronous circuits using Time Petri Net unfolding, " Unpublished manuscript, June 1995.

....distribution, and hardware design methodologies are following. With the advent of submicron VLSI technology, which will soon enable hundreds of millions of transistors to be placed on a single chip, hardware design is facing new challenges. To An earlier version of this work was presented in [Semenov Yakovlev, 1996]. cope with this complexity, and with the need to produce new VLSI designs efficiently, designers must be provided with adequate development techniques and tools. What is needed is a well integrated design system that combines simulation, synthesis, verification and testing capabilities. Such an ....

A. Semenov and A. Yakovlev. Verification of asynchronous circuits using Time Petri Net unfolding. Proc. 33rd ACM/IEEE Design Automation Conference, Las Vegas, CA, June 1996 , ACM, N.Y. pp. 59--62.

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