I.E. Sutherland, "Micropipelines", Comm. of the ACM, vol. 32, no. 6, pp. 720-738, 1989.  Home/Search   Document Not in Database   Summary   ACM   TOC   Related Articles   Check

....but not when timing constraints reduce signal interleavings (in column RTA2) The RT optimized versions of these circuits are fully testable. V. TIMING EVOLUTION IN A RING In this section, we trace the development of a simple firstin first out (FIFO) controller, similar to a micropipeline [35]. These controllers can be connected in series as shown in Fig. 6. This circuit is a simplified abstraction of a part of the RAPPID design [1] and closely follows the actual steps used to derive the final circuit. We begin with a speed independent design and review a succession of progressively ....

I. E. Sutherland, "Micropipelines," Commun. ACM, vol. 32, no. 6, pp. 720--738, June 1989.

....Simulation results are presented for several benchmark programs using the PL implementation and include a discussion of the architectural features that provide speedup within PL. Section 5 contains acknowledgements, and Section 6 presents a summary of the work. 2. Phased Logic Micropipelining [2] is a self timed methodology that uses bundled data signaling and Muller C elements [3] for controlling data movement between pipeline stages. Level Encoded Dual Rail (LEDR) signaling was introduced in [4] as a method for providing delay insensitive signaling for micropipelines. The term phase is ....

....was introduced in [4] as a method for providing delay insensitive signaling for micropipelines. The term phase is used in [4] to distinguish successive computation cycles in the LEDR micropipeline, with the data undergoing successive even and odd phase changes. The systems demonstrated in [2][4] were all linear pipelined datapaths, with some limited fork join capability also demonstrated, but with no indication of how general digital systems could be mapped to these structures. This problem was solved in [5] via a methodology termed Phased Logic (PL) which uses marked graph theory ....

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I. Sutherland, "Micropipelines", Communications of the ACM, Vol 32, No. 6, June 1989, pp. 720-738.

....wire delays completely. Thus speed independent design styles can be applied only to small chip areas. In contrast, delay insensitive design styles allow both, arbitrary logic and wire delays. Related to these classes of asynchronous design styles, architecture concepts have been developed [6] [7]. 2.1 Design Style The asynchronous FLYSIG architecture is a delay insensitive design architecture, which are independent of gate delays as well as of wire delays. This convention is the most robust one. FLYSIG is a data flow oriented architecture used for implementation of cyclic algorithms ....

I. E. Sutherland. "Micro pipelines", Communications of the ACM, 32(6), pages 720-738, June 1989

....See, for example, 7] for a description of the first asynchronous microprocessor and [3] for a brief tutorial on modern asynchronous circuit design. Such design techniques either use much more hardware than synchronous ones (self timed circuits) or are very hard to design (delay matching) [13]. The latter is not helped by the dearth of robust design tools for asynchronous systems, although work is continuing. Attempts have been made to adapt existing synchronous tools for asynchronous system use, but with limited success[5] There have been many methods created to improve the ....

I. E. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, no. 6, pp. 720-738, June 1989.

....global clock in current synchronous architectures. Together with so called data cells similar to synchronous ones, a timing cell builds a timed region. The communication between these neighboring timed regions can be configured to implement all structures provided by Sutherland s micro pipelines [13]. In contrast to these approaches we introduce a delayinsensitive, bit serial architecture. By the bit serial pipelining we compensate the area overhead arising due to delay insensitivity. 3 Asynchronous Architecture Multimedia, real time control and all kinds of sensor data preprocessing ....

I. E. Sutherland, "Micro pipelines", Communications of the ACM, 32(6), pages 720-738, June 1989

....a netlist of D flip flops and combinational logic to our self timed architecture. This means that the familiar synchronous RTL design methodology and tools used by programmable logic consumers are compatible with our proposed approach. 2. Phased Logic 2. 1 Background Sutherland s micropipelining [2] is a self timed methodology that uses bundled data signaling and Muller C elements [3] for controlling data movement between pipeline stages. Level Encoded Dual Rail (LEDR) signaling was introduced in [4] as a method for providing delay insensitive signaling for micropipelines. The term phase is ....

....was introduced in [4] as a method for providing delay insensitive signaling for micropipelines. The term phase is used in [4] to distinguish successive computation cycles in the LEDR micropipeline, with the data undergoing successive even and odd phase changes. The systems demonstrated in [2][4] were all linear pipelined datapaths, with some limited fork join capability also demonstrated, but with no indication of how general digital systems could be mapped to these structures. This problem was solved in [5] via a methodology termed Phased Logic (PL) which uses marked graph theory ....

[Article contains additional citation context not shown here]

I. Sutherland, "Micropipelines", Communications of the ACM, Vol 32, No. 6, June 1989, pp. 720-738.

....a structural HDL while concurrently affording low level control. The level of control is ideal for asynchronous circuits. Using the JBits API, an asynchronous full adder was implemented in a Virtex device. 2 Asynchronous Logic Asynchronous logic has been actively researched for several decades [6] [8] 9] However it has yet to reach mainstream use. Recently there has been a renewal of interest among the research community. Commercial products are slowly coming to market [5] 3] 7] The advantages afforded by asynchronous logic are making it an increasingly viable alternative to ....

I. Sutherland, "Micropipelines," CACM, 32(6):720-738, June 1989.

.... finally, an study of pipeline and wave pipeline power consumption on FPGAs and 1 Standard Cells is presented in [Boe95, 96] In this paper, these previous works are extended to asynchronous pipelines; in particular, the TwoPhase Bundle Convention or Micropipelines scheme proposed by Sutherland [Sut89] have been applied. This strategy was prefered to other asynchronous options because its clearness and moderate hardware requirements. Self timed systems has been repeatedly mentioned as a low power design alternative, mainly due to the elimination of the global clock lines as well as their ....

....Guild ST multiplier was constructed and measured using a XC3090PC84 100 FPGA [Xil95] The prototype made use of 310 CLBs, an excessive value because the latches were implemented using LUTs. Each asynchronous control block (ACB) is composed of a Mller C cell, an ordinary XOR gate, and a Toggle cell [Sut89]. Considering that each ACB needs three cascaded CLBs to be implemented, its size limits the practical minimum pipeline logic depth. The partitioning process into CLBs was done manually, meanwhile the placement routing was performed automatically by using the default tool parameters. The maximum ....

I. Sutherland, "Micropipelines", Communication of the ACM, vol.22, n6, pp.720734. Jun. 1989.

....same as a typical addition time performed in a system for two reasons. Firstly, the input data may not be random in nature. Garside [Gars93] has shown that the additions performed in the AMULET processor designed by 5 Furber et al. Furb93] using micropipelining concepts described by Sutherland [Suth89], had an average maximum carry propagate path almost twice as long as that expected from purely random input data, leading to a longer than expected asynchronous addition time. Secondly, additions which take a long time in a micropipelined stage will cause the following stages to be held up, and ....

Sutherland, I.E, "Micropipelines", Communications of the ACM, 32(6): pp720-738, January 1989.

.... data item dequeued, more data items available (valid get =1, empty=0) b) data item dequeued, FIFO has become empty (valid get =1, empty= 1) c) FIFO empty, no data item dequeued (valid get =0, empty=1) The asynchronous interfaces use 4 phase communication with single rail bundled data ( 8] [15]) Bundled data is a common scheme where a worst case matched control signal (e.g. put req ) indicates when data is valid (put data ) The sender starts a put operation (Fig. 3c) by placing a data item on put data and requesting the FIFO to enqueue it on put req . The enqueuing completion is ....

....(as in Carloni) to limit the wire lengths between stages to short hops. Also, as in the dual rail case, inserting ARS s can increase the throughput on the interfaces. A chain of asynchronous relay stations can be directly implemented by using a standard asynchronous FIFO called a micropipeline ([15], 14] Unlike the synchronous data packets, the asynchronous ones do not need a validity bit: the presence of valid data Throughput Latency 8 bit data items 16 bit data items 8 bit data items Ve r s on 4 place 8 place 16 place 4 place 8 place 16 place 4 place 8 place 16 place put get put get ....

I. E. Sutherland, "Micropipelines", Communications of the ACM, 32(6), pp. 720-738, June 1989.

....provides a means for the selftimed logic to detect completion of a logic function for each data token. Otherwise, it would not be possible to separate two consecutive tokens that happen to have the same value. Several methods of designing 4 phase dual rail logic have been developed [1] 5] [15] In these design styles the functional delay through a logic block for a spacer token is approximately the same as for a data token. Other 4 phase dual rail design styles use a control signal to reset, or precharge all gates in the function block in parallel before accepting the next data token ....

I. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, 1989, pp. 720-738.

.... Asynchronous systems are typically classified by their timing model, signalling protocol and by the method used for their design and implementation [6, 7, 8] For brevity, this paper assumes familiarity with the bounded delay and delay insensitive timing models, Muller C gates and macromodules [5, 6, 7, 8, 9, 10]. 2.1 Signalling Protocols Asynchronous circuits generally use an inter element signalling scheme to act as a protocol layer for all transitions; these are self timed circuits. Designs based on macromodules, including micropipelines, are among these [5, 7, 9, 10] Signalling protocol control ....

....gates and macromodules [5, 6, 7, 8, 9, 10] 2.1 Signalling Protocols Asynchronous circuits generally use an inter element signalling scheme to act as a protocol layer for all transitions; these are self timed circuits. Designs based on macromodules, including micropipelines, are among these [5, 7, 9, 10]. Signalling protocol control paths typically use event logic, an event being a logic level transition. a) Acknowledge Data Request Data Receive Send Null Recover False 0 10 Null 00 01 True 1 Timing Code Words Channel Parameters Number of data bits : n Total Wires: 2n 1 Data ....

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Sutherland, I. E. (1989), "Micropipelines", Communications of the ACM, 32(6): 720-38.

....have been proposed to design asynchronous datapath components. Most fall into one of two categories, depending on how completion is determined: bundled data and completion detection. A bundled data design uses a worst case model delay, designed to exceed the longest path through the subsystem [6, 1]. This delay may be an inverter chain or a replicated portion of the critical path. This method has been widely used [4, 3, 2, 5] The main advantage is that a standard synchronous (i.e. non hazard free) single rail implementation may be used, so implementations are easy to design, and have low ....

I.E. Sutherland, "Micropipelines", in Communications of the ACM, vol. 32, June 1989, pp. 720--738.

....Van Berkel s method also yields quasi delay insensitive circuits. Other translation methods from a CSP like language to a (quasi ) delay insensitive circuit can be found in [40, 41] 12 4 A Typical Asynchronous Design In this section we present a typical asynchronous design, a micropipeline [42]. The circuit uses single rail encoding with the two phase signaling protocol to communicate data between stages of the pipeline. The control circuit for the pipeline is a delay insensitive circuit. First we present the primitives for the control circuit, then we present the latches that store the ....

....graph for the join is produced by replacing the bidirectional arcs by unidirectional arcs. There are many implementations of the C element. We have given two popular CMOS implementations in Figure 5. Implementation (a) is a conventional pull up pull down implementation suggested by Sutherland [42]. Implementation (b) is suggested by Van Berkel [29] Each implementation has its own characteristics. Implementation (b) is the best choice for speed and energy efficiency [43] P2 N2 N1 N3 N4 N5 P5 P3 P4 P6 N6 V DD V DD P1 p2 N2 N1 P6 N6 P1 b a a b a a b c c a b a a ....

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I. E. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, pp. 720--738, June 1989.

....and wires. Delay insensitive circuits are generally considered the most difficult, expensive and elusive circuits to design. Only a few truly delay insensitive circuit designs are known. Fundamental mode circuits typically use matched delay lines to provide a local time reference for each circuit [4] and speed independent circuits must make assumptions about the insignificant propagation delay of the wires in the circuit. These attempts to eliminate time dependencies are nearly always expressed within the traditional context of Boolean logic. They focus on designing Boolean logic circuits ....

Ivan E. Sutherland, "Micropipelines", Communications of the ACM , Vol. 32, No. 6, June

.... set and the use of transparent compilation are modelled on the Philips Tangram system [16] Balsa differs from Tangram in a number of respects: The channel semantics have been extended to include the enclosure of commands within a channel receive command allowing the synthesis of Micropipeline [17], data driven push like structures, in addition to the normal pull style control driven circuits normally produced. The handshake component library has been extended to include components with a greater degree of parameterization in order to take advantage of conventional forms of automated ....

Sutherland, I.E., "Micropipelines". Communications of the ACM, 32(6), June 1989, pp. 720-738.

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I.E. Sutherland, "Micropipelines", Comm. of the ACM, vol. 32, no. 6, pp. 720-738, 1989.

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I. E. Sutherland, "Micropipelines," Commun. ACM, vol. 32, pp. 720--738, 1989.

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I. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, pp. 720-738, 1989.

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Sutherland, I.E. "Micropipelines." Communications. ACM. vol. 32 No. 6 pp. 72073.

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I. E. Sutherland, "Micropipelines," Communications of the ACM, June 1989.

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I. E. Sutherland, "Micropipelines," Communications of the ACM, June 1989.

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I.E. Sutherland, "Micropipelines", Communication of the ACM, vol. 32, no. 6, pp. 720-738, June 1989

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Ivan E. Sutherland, "Micropipelines", Communications of the ACM , Vol. 32, No. 6, June 1989, pp. 720-738.

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I.E. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, no. 6, pp 720-738, June t989.

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