L. Lavagno, M. Kishinevsky, and A. Lioy, "Testing redundant asynchronous circuits by variable phase splitting," in Proc. European Design Automation Conf., Sept. 1994. 19 Home/Search Document Details and Download
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This paper is cited in the following contexts:
Synthesis of Asynchronous Circuits for Stuck-at and Robust.. - Nowick, Jha, Cheng (1995) (2 citations) (Correct)
....this fault model is that since asynchronous interface circuits usually have strict delay requirements, it is desirable to detect any abnormality in their temporal behavior. Another interesting method has also been developed, where independent control of both phases of each variable is assumed [7]. The aim of this paper is to synthesize hazard free asynchronous circuits which are also completely testable under the stuck at or the robust path delay fault models. Both fault models are treated similarly; however, the latter model may require slightly greater area overhead. As in [4] we ....
L. Lavagno, M. Kishinevsky, and A. Lioy, "Testing redundant asynchronous circuits by variable phase splitting," in Proc. European Design Automation Conf., Sept. 1994. 19
Progress Report on Research on the Testing of Asynchronous Circuits - Liebelt (1995) (1 citation) (Correct)
....logic implementations to produce a multi level implementation which is both hazard free and Robust Path Delay Fault Testable. With the inclusion of suitable scan paths the combinational logic can therefore be delay fault tested and the operation of the asynchronous circuit verified. In [LKL94] Lavagno et al. show that by phase splitting (allowing literals and their complements to be independently controlled at the input to combinational logic functions) any combinational logic can be converted into a positive unate, hence prime irredundant, hence RPDFT circuit without requiring any ....
Luciano Lavagno, Michael Kishinevsky, and Antonio Lioy. Testing redundant asynchronous circuits by variable phase splitting. In Proc. European Design Automation Conference (EURO-DAC), pages 328--333. IEEE Computer Society Press, September 1994.
A Proposal for Research on the Testability of Asynchronous Circuits - Liebelt (1998) (Correct)
....hazard free logic implementations to produce a multi level implementation which is both hazard free and Robust Path Delay Fault Testable. With the inclusion of suitable scan paths the combinational logic can therefore be delay fault tested and the operation of the asynchronous circuit verified. In [32] Lavagno et al. show that by phase splitting (allowing literals and their complements to be independently controlled at the input to combinational logic functions) any combinational logic can be converted into a positive unate, hence prime irredundant, hence RPDFT circuit without requiring any ....
L. Lavagno, M. Kishinevsky, and A. Lioy, "Testing redundant asynchronous circuits by variable phase splitting," in Proc. European Design Automation Conference (EURO-DAC), pp. 328--333, IEEE Computer Society Press, Sept. 1994.
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