S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, November 1993.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....Ops, Config , to a new global history, TransSeq , Ops , Con fig in which TransSeq is legal. 4 RELATED WORK We focus on papers that specify and prove a complete protocol correct, rather than on efforts that focus on describing many alternative protocols and consistency models, such as [2], 12] There is a large body of literature 4 on the subject of formal protocol verification, which we have classified into a taxonomy along two independent axes: automation and completeness [27] We distinguish verification methods based on the level of automation they support: manual, ....

S.V. Adve, "Designing Memory Consistency Models for SharedMemory Multiprocessors," PhD thesis, Computer Sciences Dept., Univ. of Wisconsin-Madison, Nov. 1993.

....as write buffers and caching, have introduced complexity in supporting sequential consistency as a model of choice on shared memory multiprocessors. These have led to extensive work in specifying, defining, and implementing various memory consistency models on modern shared memory multiprocessors [2, 3, 4, 44, 45, 46, 133, 147]. Relaxed memory models have been proposed to enable the use of more optimizations by relaxing the limitations on the ordering of memory operations as imposed by strict memory mod 31 els such as sequential consistency. While sequential consistency requires the illusion of program order and ....

....ALPHA architecture [28] and SYNC in the PowerPC [31] In all cases, there is a single point (at least one) where all preceding operations have been completed and no succeeding operations have been executed. A tutorial on shared memory models by Adve and Gharachorloo [3] and their respective theses [2, 44] provide detailed background into various memory consistency models. Figure 2 2: Conceptual view of sequential consistency. Each processor interacts with shared memory through a single switch in a one at a time fashion. P 0 P 1 P n 1 32 Caching is a popular technique to reduce long latency ....

Sarita V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin, Madison, WI, 1993.

....to shared variables. This is more evident if the shared memory is not centralized but distributed among a number of processors, i.e. we have distributed shared memory (DSM) There has been a number of proposals and implementations of DSM systems providing di erent semantics, or consistency models [1, 2, 4, 6, 12]. The consistency memory models proposed in the literature can be broadly classi ed into strong and weak memory mod This work is partially supported by the CICYT under grant TEL99 0582 and the Comunidad Aut onoma de Madrid under grant CAM 07T 00112 1998. els. The strong memory models are ....

S. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, 1993.

....are too strong. This is because the conditions for RC affect not only conflicting but all ordinary accesses [5] While it is easy to envision a weaker version of RC in which restrictions apply only to conflicting ordinary accesses, a hardware implementation of such is by no means obvious [1]. Fig. 1 shows an example of two threads competing for access to a critical section. Suppose that the leftmost thread is granted access first. In the figure, arrows show some of the ordering restrictions imposed by RC. Conflicting accesses to location X are successfully made non competing by ....

S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. Ph.D. thesis, Univ. of Wisconsin at Madison, December 1993.

....to shared variables. This is more evident if the shared memory is not centralized but distributed among a number of processors, i.e. we have distributed shared memory (DSM) There has been a number of proposals and implementations of DSM systems providing di erent semantics, or consistency models [1, 2, 4, 6, 12]. The consistency memory models proposed in the literature can be broadly classi ed into strong and weak memory mod This work is partially supported by the CICYT under grant TEL99 0582 and the Comunidad Aut onoma de Madrid under grant CAM 07T 00112 1998. els. The strong memory models are ....

S. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, 1993.

....the application programmers. This hardware software interface has two primary dimensions that influence the hardware design: a memory consistency model and a mechanism for maintaining memory coherence. The consistency model determines the extent to which memory references are allowed to overlap [1, 2, 3, 4, 5]. A strong consistency Figure 1: Key dimensions of the hardware software interface. Instruction Set Memory Consistency Model Coherence Protocol Branch ALU Load Store Sync. Instructions Architecture Shared Memory Programming Model (a) Constituents of the programming model Ivy Munin ....

....As a result of these highlevel properties there are many implications for the hardware implementation that deal with the issues of deadlock, livelock, fairness and starvation. These high level correctness properties provide a set of sufficient conditions for memory coherence and consistency [24,25,16,2,3,4]. Data coherence. A memory system is coherent if the value returned by a load is always the value from the latest store to the same memory location. Preservation of program order. The memory system will impose a serial order on all memory operations to the same address. The order in which memory ....

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S.V.Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors.PhDthesis,Computer Sciences Department, University of WisconsinMadison, December 1993.

....with respect to all processors. A write is globally performed when it is performed. A read is globally performed when it is performed and when the write whose value it reads is performed. Thus, a write or a read is globally performed when the value written or read is observed by all processors [Adv93] 1.2.3 Processor Consistency Processor consistency [Goo89, GLL 90] was proposed to relax the program order constraints in the case of a write followed by a read operation to a di#erent location. It allows the read operation to bypass the write before the write is serialized or made visible ....

....data accesses have to be performed before their subsequent synchronization operation is performed. Weak consistency may provide better performance than sequential consistency by allowing operations between two synchronization operations to be reordered, executed in parallel, and non atomically [Adv93] 1.2.5 Release Consistency Release consistency [GLL 90] is an extension of weak consistency. Release consistency classifies operations on shared memory into two categories, special and ordinary. Special operations also are classified into sync and nsync. Sync operations are either release ....

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S. Adve. Designing Memory Consistency Models for SharedMemory Multiprocessors. PhD thesis, University of WisconsinMadison, 1993.

....as an abstraction layered upon this message passing substrate. The FSMs at each level of the memory hierarchy are responsible for implementing the coherence protocol. The coherence protocol is a set of rules that, when followed by each computing node, ensure a consistent view of the memory system [4, 5, 6, 7]. The coherence mechanism may be implemented in a variety of ways, through either software, hardware, or a combination of the two. A hardware based coherence mechanism provides better performance at the expense of losing the flexibility that is afforded by software based approaches. Bus based ....

S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, Computer Sciences Department, University of Wisconsin-Madison, December 1993.

....as an abstraction layered upon this message passing substrate. The FSMs at each level of the memory hierarchy are responsible for implementing the coherence protocol. The coherence protocol is a set of rules that, when followed by each computing node, ensure a consistent view of the memory system [4, 5, 6, 7]. The coherence mechanism may be implemented in a variety of ways, through either software, hardware, or a combination of the two. A hardware based coherence mechanism provides better performance at the expense of losing the flexibility that is afforded by software based approaches. Bus based ....

S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, Computer Sciences Department, University of Wisconsin-Madison, December 1993.

.... TransSeq,Ops,Config , to a new global history, TransSeq ,Ops ,Config in which TransSeq is legal. 4 Related Work We focus on papers that specify and prove a complete protocol correct, rather than on efforts that focus on describing many alternative protocols and consistency models, such as [1, 10]. There is a large body of literature on the subject of formal protocol verification 4 which we have classified into a taxonomy along two independent axes: automation and completeness [23] We distinguish verification methods based on the level of automation they support: manual, semi automated ....

S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, Computer Sciences Department, University of Wisconsin--Madison, Nov. 1993.

....4 most of their algorithms are tailored to detect and handle excess barriers introduced during compilation. y In contrast, we present algorithms to detect and transform barriers, pairwise synchronization, and critical sections. We explain these algorithms using a framework introduced by Adve [Adv93] for reasoning about memory models. We also present new algorithms to reduce synchronization and data communication by restructuring computation. These algorithms are based on two new computation transformations we have developed: postponing and relocating computation. Contribution 3 A set of ....

....the efficacy of this approach will be affected when applied to non object based programs, for which the static analysis is likely to be less precise. Several of the algorithms presented in this chapter have been explained using a framework for reasoning about memory models introduced by Adve [Adv93] Adve has used this framework to explore system optimizations that do not violate sequential consistency, based on information supplied by the programmer [Adv96] In contrast, we use her framework to determine excess synchronization or synchronization that is stronger than necessary. Adve et. ....

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S.V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin, Madison, December 1993.

.... consistency within the memory system itself [14, 15] work on testing the serializability of database transactions [31] work on detecting data races (e.g. 2, 23, 28, 29] work on proving that weak memory systems provide sequential consistency for programs that are free of data races (e.g. [1, 20, 21]) work on testing uniprocessor memories [9] work on algorithms for testing data structures on uniprocessors (e.g. 10] work on verifying specific properties of cache coherence protocols (e.g. 32] and the references therein) work on computing with faulty shared memories [4] work on ....

S. V. Adve, Designing Memory Consistency Models for Shared-Memory Multiprocessors, PhD thesis, University of Wisconsin-Madison, Dec. 1993.

.... the different processors is provided by sequential consistency [5] Since this results in limited performance due to a high message overhead and strict ordering requirements a variety of weaker protocols have been proposed which improve concurrency and reduce the amount of data to be transferred [1]. This is accomplished by restricting the programming model or by requiring the programmer to insert annotations to initiate memory updates. Any program conforming to these rules then executes as if it were running on a sequentially consistent memory. Figure 1 shows 3 pages in the shared memory ....

Adve, Sarita V.: Designing Memory Consistency Models For Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, Department of Computer Science, (1993).

....In order to provide the abstraction of a shared memory or global address space, some kind of coherence protocol must be implemented to coordinate the access to the memory. A great variety of protocols serving different needs on consistency have been proposed and analyzed in the literature [30, 15]. Current microprocessors driven by the fast development of workstation technology are taking over the role of processing nodes on most available parallel computers [29, 25, 13] Modern RISC designs usually provides 2 hierarchies of memory caches to interface the high bandwidth requirements for ....

.... different processors is provided by sequential consistency [23] Since this results in limited performance due to a high message overhead and strict ordering requirements a variety of weaker protocols have been proposed which improve concurrency and reduce the amount of the data to be transferred [30]. This is accomplished by restricting the programming model or by requiring the programmer to insert annotations to initiate memory updates. Any program conforming to these rules then executes as if it were running on a sequentially consistent memory. 2.1.1 Granularity and False Sharing A Write ....

Sarita V. Adve. Designing Memory Consistency Models For Shared-Memory Multiprocessors. Phd dissertation, University of Wisconsin-Madison, Department of Computer Science, 1993.

....writes to reads (Section 3.1) while others aggressively relax the order among all normal reads and writes (Section 3.2) More details about these models and references to primary sources can be found in an excellent relaxed memory model tutorial by Adve and Gharachorloo [2] their Ph.D. theses [1,4], and Collier s tools for distinguishing memory models (www.infomall.org diagnostics archtest.html) For this reason, many academics, including myself, have advocated relaxed models over SC. The advent of speculative execution has changed my mind. Section 4 argues that multiprocessor hardware ....

Sarita V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, Computer Sciences Department, University of Wisconsin--Madison, November 1993.

....by an IBM graduate fellowship. The work at Rice was supported in part by the National Science Foundation under Grant No. CCR 9502500 and CCR 9410457, and the Texas Advanced Technology Program under Grant No. 003604 016 and 003604 025. This work is a distillation of the author s Ph.D. thesis [1]. consistency [28] ensures that all memory operations in an execution will appear to execute one at a time (or atomically) and memory operations of a single process will appear in program order. While sequential consistency provides an intuitive programming interface, its requirements of program ....

....This paper focuses on an alternate, programmer based, approach. This approach relies on obtaining information from the programmer that identifies parts of the program where an optimization (e.g. out of order or non atomic execution of memory operations) will not violate sequential consistency [1, 5, 6, 20, 22, 18]. Based on the information, the system applies the appropriate optimization to the appropriate parts of the program. As long as the information given is correct, programmers can continue to assume sequential consistency, while simultaneously benefiting from performance enhancing system ....

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S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, Computer Sciences Department, University of Wisconsin-Madison, December 1993. Available as Technical Report #1198.

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Sarita V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, Computer Sciences Technical Report #1198, University of Wisconsin - Madison, December 1993.

....be replaced by a hardware fence. For HPF, the parallelizing compiler itself inserts synchronization, and must insert hardware fences at these points. A more comprehensive description of how to port data racefree properly labeled programs to common hardware memory consistency models appears in [28], 29] VI. Concluding Remarks This paper provides an overview of recent advances in memory consistency models, covering hardware, compilers, and programming environments. Recent hardware optimizations have significantly narrowed the hardware performance gap between various consistency models, ....

S. V. Adve, Designing Memory Consistency Models for SharedMemory Multiprocessors. PhD thesis, Computer Sciences Department, University of Wisconsin-Madison, December 1993.

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S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, November 1993.

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S.V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, 1993.

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S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, November 1993.

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Sarita V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, Computer Sciences Department, University of WisconsinMadison, December 1993

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S. Adve, "Designing Memory Consistency Models for Shared-memory Multiprocessors", Computer Sciences Technical report #1198, University of Wisconsin-madison, Dec. 1993.

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S.V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, 1993.

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S. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. Technical Report 1198, Computer Science Department, University of Wisconsin-Madison, December 1993. Ph.D. Thesis.

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