M. T. Raghunath and A. Ranade. Designing interconnection networks for multi-level packaging. In Proc. of the Supercomputing, pages 772--781, 1993. 19  Home/Search   Document Not in Database   Summary   Related Articles   Check

....to be interconnected by using fewer network interfaces and network routers leading to a more cost effective design. In recent years there has been a lot of research related to designing processor clustered based systems. However, most of these research have emphasized on packaging aspects [3, 14, 10]. These results are geared towards deriving optimal inter cluster topologies under packaging and pinout constraints. While deriving such optimal topologies researchers have primarily emphasized on the load on network bisection and evaluated different topologies with respect to average message ....

....channels per cluster. Typically, most systems have i = 1 2, this value being limited by the maximum available router pinout [3] 3 Processor cluster organizations Processor cluster based architectures have been motivated by the convenience of packaging multiple processors into a single cluster [3, 14]. Details about the topology inside the cluster, the memory organization, impact of this organization on system performance etc. have not been addressed. Thus, there is a need to determine whether there is a requirement for tightly coupled clusters that can take advantage of the higher integration ....

M. T. Raghunath and A. Ranade. Designing interconnection networks for multi-level packaging. In Proc. of the Supercomputing, pages 772--781, 1993. 19

....Abraham and Padmanabhan s study [1] under a constant pinout from a processing node. Agrawal s [2] analysis of k ary n cube networks considers three different constraints: constant bisection width, constant channel width, and constant pinout while considering node and wire delays. However, Ranade [21, 22] and Yew [13] have argued that neither Dally s VLSI model with limited bisection bandwidth nor the limited pinout model as proposed in [1, 2] is adequate while designing very large systems. Both models confine to only one level of packaging hierarchy whereas large systems typically employ several ....

....VLSI model with limited bisection bandwidth nor the limited pinout model as proposed in [1, 2] is adequate while designing very large systems. Both models confine to only one level of packaging hierarchy whereas large systems typically employ several levels of packaging. It was demonstrated in [22] that while designing a large multiprocessor system with multiple levels of packaging, multi level hierarchical clustered architecture can be an advantage. The architectural levels can be chosen to closely match the packaging hierarchy leading to better designs. A multi level architecture also ....

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M. T. Raghunath and A. Ranade. Designing interconnection networks for multi-level packaging. In Proc. of the Supercomputing, pages 772--781, 1993.

....believed that most systems in the near future will fit in two hierarchies. Moreover the techniques which work for two level hierarchies can be easily extended to design more levels. Examples of previous work in this area include two level systems based on hypercube and other network topologies[5, 15, 18], MINs and n hop networks [18] twolevel systems with k ary n cube topologies[2] and combination of bus and mesh hypercube networks[10] However, most of these analyses either did not consider packaging and interconnecting constraints, or provided guidelines based only on fixed board sizes with ....

....near future will fit in two hierarchies. Moreover the techniques which work for two level hierarchies can be easily extended to design more levels. Examples of previous work in this area include two level systems based on hypercube and other network topologies[5, 15, 18] MINs and n hop networks [18], twolevel systems with k ary n cube topologies[2] and combination of bus and mesh hypercube networks[10] However, most of these analyses either did not consider packaging and interconnecting constraints, or provided guidelines based only on fixed board sizes with fixed pinouts, not considering ....

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M. T. Raghunath and Abhiram Ranade. Designing interconnection networks for multilevel packaging. In Proc. of the Supercomputing, pages 772--781, 1993.

....[1] under a constant pinout from a processing node. Agrawal s [2] analysis of the same class of networks considers three different constraints: constant bisection width, constant channel width, and constant pinout and is based on a more comprehensive model of node and wire delays. However, Ranade [23, 24] and Yew [15] argued that neither Dally s VLSI model with limited bisection bandwidth nor the limited pinout model as proposed in [1, 2] is adequate for very large systems. Both models confine to only one level of packaging hierarchy whereas large systems typically employ several levels of ....

....neither Dally s VLSI model with limited bisection bandwidth nor the limited pinout model as proposed in [1, 2] is adequate for very large systems. Both models confine to only one level of packaging hierarchy whereas large systems typically employ several levels of packaging. It was demonstrated in [24] that considering two level hierarchical clustered systems widen the scope of the design space. The architectural levels can be chosen to closely match the packaging hierarchy leading to better designs. A variety of two level hierarchical configurations have been proposed by researchers in the ....

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M. T. Raghunath and A. Ranade. Designing interconnection networks for multi-level packaging. In Proc. of the Supercomputing, pages 772--781, 1993.

....a new framework for designing and developing large hierarchical architectures. We consider a packaging technology with two levels: processors in the parallel computer are organized into a number of boards(clusters) and the boards are then connected through inter board wires. It has been shown [5] that a common characteristic of most packaging technologies is a progressive increase in costs and decrease in capacities as we go up the packaging hierarchy. In our framework we therefore put more importance on optimizing the inter board costs. Among other things the design model allows varying ....

....the packaging hierarchy. In our framework we therefore put more importance on optimizing the inter board costs. Among other things the design model allows varying board sizes, a choice of reasonable channel widths, and flexible pinout with alternate pinout technologies. Previous work in this area [3, 5] have developed guidelines based only on fixed board sizes with fixed pinouts, not considering changes in board sizes and alternate pinout technologies. The changes in processor and interconnection technology and its relation to packaging technology in designing systems has also not been studied ....

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M. T. Raghunath and A. Ranade. Designing interconnection networks for multi-level packaging. In Proc. of the Supercomputing, pp. 772--781, 1993.

.... scalable systems using processor clusters include cluster of processors with buses and MINs[9] local and global meshes[7] and two level systems based on hypercube and other network topologies[12, 17] Other researchers have studied the design problem under very realistic packaging constraints [14, 5, 20] and proved that under such conditions clustering becomes more useful. However, these works do not demonstrate the merits of clustering in scaling systems. Although some recent systems like the Cray T3D [8] DASH [13] are being built based on the clustering approach, there is no formal study to ....

....of the base system. This leads us to an interesting question: given that either system can be built, which one of these would be more cost effective and deliver lower average message latency To compare costs here we use the metric of interconnect wiring costs[5] It has been demonstrated in [20] that such costs in the inter cluster network constitute a significant fraction of the total system costs. We determine these cost figures for both systems, by first computing the total number of channels in the inter cluster network (4k(k Gamma 1) This is multiplied by the channel width (W ....

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M. T. Raghunath and A. Ranade. Designing interconnection networks for multi-level packaging. In Proc. of the Supercomputing, pages 772--781, 1993.

....The authors are with the Department of Computer and Information Science, The Ohio State University, Columbus, OH 43210 1277. Email: fbasak,pandag cis.ohio state.edu. stant bisection width, constant channel width, and constant pinout while considering node and wire delays. However, Ranade [18] [19] and Yew [12] have argued that neither Dally s VLSI model with limited bisection bandwidth nor the limited pinout model as proposed in [1] 2] is adequate while designing very large systems. Both models confine to only one level of packaging hierarchy whereas large systems typically employ ....

....VLSI model with limited bisection bandwidth nor the limited pinout model as proposed in [1] 2] is adequate while designing very large systems. Both models confine to only one level of packaging hierarchy whereas large systems typically employ several levels of packaging. It was demonstrated in [19] that while designing a large multiprocessor system with multiple levels of packaging, multi level hierarchical clustered architecture can be an advantage. The architectural levels can be chosen to closely match the packaging hierarchy leading to better designs. A multi level architecture also ....

[Article contains additional citation context not shown here]

M. T. Raghunath and A. Ranade. Designing interconnection networks for multi-level packaging. In Proc. of the Supercomputing, pages 772--781, 1993.

....or received from a processor. This can lead to much of the communication bandwidth offered by the expensive fast interconnect to remain unutilized. With advancements in VLSI and packaging technologies it has become cost effective to integrate multiple processing elements into a chip or a board [6, 7]. This is leading to the development of parallel systems using such processor clusters as building blocks instead of single processors[3] Previous research on clustered systems have focused mostly on proposing and proving different interconnection topologies[4] and studying the design problem ....

.... parallel systems using such processor clusters as building blocks instead of single processors[3] Previous research on clustered systems have focused mostly on proposing and proving different interconnection topologies[4] and studying the design problem under very realistic packaging constraints [1, 7]. Such processor clustering also demonstrates potential to alleviate the network under utilization problem by allowing more number of processors to use a given set of network resources. However, no formal study is available in the literature which shows the benefits of processor clustering towards ....

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M. T. Raghunath and A. Ranade. Designing interconnection networks for multi-level packaging. In Proc. of the Supercomputing, pages 772--781, 1993.

....to be a dominant factor for poor utilization of network resources in current generation parallel systems. Advancements in VLSI and packaging technologies is now allowing the integration of a small number of processing elements, interconnected through a network, onto a single multi chip or a board [15, 22] module. Such processor cluster modules are being increasingly used instead of single processors to build variety of computing vehicles such as servers, workstations, etc. This is leading to greater demand and production for such modules, consequently bringing down perunit cost. Larger systems are ....

.... systems using processor clusters[4, 8] Previous research on using processor clusters for building large parallel systems have mainly focused on proposing and proving different interconnection topologies[10, 20, 21] and studying the design problem under very realistic packaging con1 straints [5, 22]. Such processor clustering also demonstrates potential to alleviate the network under utilization problem by allowing more number of processors to use a given set of network resources. However, no formal study is available in the literature which shows the benefits of processor clustering towards ....

[Article contains additional citation context not shown here]

M. T. Raghunath and A. Ranade. Designing interconnection networks for multi-level packaging. In Proc. of the Supercomputing, pages 772--781, 1993.

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