H. Iba, M. Iwata, and T. Higuchi. Machine learning approach to gate-level evolvable hardware. In T. Higuchi and M. Iwata, editors, Proceedings of the 1st International Conference on Evolvable Systems: From Biology to Hardware, volume 1259 of Lecture Notes in Computer Science, pages 327--343, Heidelberg, 1997. Springer-Verlag.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....1. Introduction The evolution of digital circuits has been intensively studied to discern generalisable principles of design and thus to allow one automatically to produce large and efficient electronic circuits. Digital electronic circuits have been evolved intrinsically [9] and extrinsically [6, 4, 5, 18, 7]. The former is associated with an evolutionary process in which each evolved electronic circuit is built and tested on hardware, while the latter refers to circuit evolution implemented entirely in software using computer simulations. A major problem in the evolutionary design of electronic ....

H. Iba, M. Iwata, and T. Higuchi. Machine learning approach to gate-level evolvable hardware. In T. Higuchi and M. Iwata, editors, Proceedings of the 1st International Conference on Evolvable Systems: From Biology to Hardware, 327--343, Heidelberg, 1997. Springer-Verlag.

.... or it may be in an adaptive context [7] 20] Other workers have employed evolutionary algorithms to optimise coefficients together with add and shift operations in so called multiplier less designs [18] 19] 23] The pioneering concept of gate level evolution of digital functions was developed in [9]. In [17] the authors generalised the concept of gate level evolution to the socalled functional level, and they showed how it was possible to carry out adaptive equalisation on a communications channel with superior bit error rates to the conventional least mean squares method. One of the ....

Iba H., Iwata M., and Higuchi T., "Machine Learning Approach to Gate-Level Evolvable Hardware", in Higuchi T., Iwata M., and Liu W., (eds.), Proc. of The 1st International Conference on Evolvable Systems: From Biology to Hardware (ICES96), LNCS, Vol. 1259, Springer-Verlag, Heidelberg, pp. 327 -- 343, 1997.

....an autonomous process in which a highly efficient circuit may occur in a population of interacting instances of a logic function. The possibilities for automatic design of electronic circuits using evolutionary algorithms have been explored in the analogue [10, 23, 18, 2, 30, 22, 24] and digital [5, 4, 15, 6, 8, 13] domains. In general the methodology of evolving circuitry and machinery used is most easily described in the framework of a simple evolutionary algorithm. A disadvantage of such an approach however is that the evolution may end up with a functionally incorrect evolved circuit. This may cause a ....

H. Iba, M. Iwata, and T. Higuchi. Machine learning approach to gate-level evolvable hardware. In T. Higuchi and M. Iwata, editors, Proceedings of the 1st International Conference on Evolvable Systems: From Biology to Hardware, volume 1259 of Lecture Notes in Computer Science, pages 327--343, Heidelberg, 1997. Springer-Verlag.

....1. Introduction The evolution of digital circuits has been intensively studied to discern generalisable principles of design and thus to allow one automatically to produce large and efficient electronic circuits. Digital electronic circuits have been evolved intrinsically [9] and extrinsically [6, 4, 5, 18, 7]. The former is associated with an evolutionary process in which each evolved electronic circuit is built and tested on hardware, while the latter refers to circuit evolution implemented entirely in software using computer simulations. A major problem in the evolutionary design of electronic ....

H. Iba, M. Iwata, and T. Higuchi. Machine learning approach to gate-level evolvable hardware. In T. Higuchi and M. Iwata, editors, Proceedings of the 1st International Conference on Evolvable Systems: From Biology to Hardware, volume 1259 of Lecture Notes in Computer Science, pages 327--343, Heidelberg, 1997. Springer-Verlag.

....is a process of evolving configurations of logic gates for some prespecified computational program. Often the aim is for a highly efficient electronic circuit to emerge in a population of instances of the program. Digital electronic circuits have been evolved intrinsically [1] and extrinsically [2 6]. The former is associated with an evolutionary process in which each evolved electronic circuit is built and tested on hardware, while the latter refers to circuit evolution implemented entirely in software using computer simulations. A possible way to study the evolvability of digital circuits ....

Iba, H., Iwata, M., Higuchi, T.: Machine learning approach to gate-level evolvable hardware. In Higuchi, T., Iwata, M., eds.: Proceedings of the 1st International Conference on Evolvable Systems: From Biology to Hardware. Heidelberg, Springer-Verlag (1997) 327--343.

....A central idea of this approach is to represent each possible electronic circuit as chromosome in an evolutionary process in which the standard genetic operators such as initialisation, recombination, selection are carried out. The circuits may be evaluated using software simulation models [1] [2], 3] 4] or alternatively evolved entirely in hardware [5] 6 , 7] 8] In this paper, we limit our focus to combinational logic circuits, which contain no memory elements. Such circuits contain no feedback paths. Note that this approach can be easily extended for the combinational ....

Iba H., Iwata M., and Higuchi T. (1997). Machine Learning Approach to Gate-Level Evolvable Hardware in Proc. of The 1 st Int. Conf. on Evolvable Systems: From Biology to Hardware (ICES96), Lecture Notes in Computer Science, Eds.: Higuchi T. et al, Vol. 1259, Publisher: Springer-Verlag, Heidelberg, pp. 327 -- 343.

....marked effect on the success of the evolutionary process. 0. Introduction There is, at the current time, a growing interest in designing electronic circuits using evolutionary techniques [11] Koza [8] showed how simple digital circuits could be evolved using Genetic Programming, and Iba et al. [5] showed how it was possible to design circuits by evolving the functionality and connectivity of interconnected AND, OR, and NOT gates for intended use on a programmable logic array device (PLA) The group at EPFL developed a cellular automaton in hardware using Xilinx XC6216 Field Programmable ....

Iba H., Iwata M., and Higuchi T., Machine Learning Approach to Gate-Level Evolvable Hardware, in [B], pp. 327 - 343.

....which is considerably larger and richer than the traditional human, top down, difference equation method. Secondly to see how effective a microscopic number of logic gates might be in a filtering task. The pioneering concept of gate level evolution of digital functions was developed in [7]. In [13] the authors generalised the concept of gate level evolution to the so called functional level, and they showed how it was possible to carry out adaptive equalisation on a communications channel with superior bit error rates to the conventional least mean squares method. Their method was ....

Iba H., Iwata M., and Higuchi T., Machine Learning Approach to Gate-Level Evolvable Hardware, in Higuchi T., Iwata M., and Liu W., (Editors), Proceedings of The First International Conference on Evolvable Systems: From Biology to Hardware (ICES96), Lecture Notes in Computer Science, Vol. 1259, Springer-Verlag, Heidelberg, pp. 327 -- 343, 1997.

....learning [16] For this task, there are algorithmic approaches which, although complete, suffer from computational complexity. We have chosen a stochastic method, the evolutionary method, which use probabilistic search and is more efficient than algorithmic approach but does not assure completeness[10]. They are also well adapted to robotics task for which many Boolean functions are solutions. Unfortunately evaluating the pair sensor motion at each step of the robot motion suffers from the problem of local maxima. The learned behavior settles into a very suboptimal policy that prevents the ....

Hitoshi Iba and Masaya Iwata. Machine learning approach to gate-level evolvable hardware. In Proceeding of the First International Conference on Evolvable Systems: from Biology to Hardware. Springer Verlag, 1996.

....possible electronic circuit can be represented as a chromosome in an evolutionary process in which the standard genetic operations over the circuits, such as initialization, recombination, elitism, selection are carried out. The evolving circuits may be evaluated using software simulation models [4, 7, 8, 12], or in some cases implemented directly in hardware [2, 11] A number of investigations have been carried out for synthesis of binary logic circuits [4, 7] Multiple Valued (MV) Logic refers to the adoption of logic systems having more than two levels [3, 9] It is generally felt that MV logic ....

....recombination, elitism, selection are carried out. The evolving circuits may be evaluated using software simulation models [4, 7, 8, 12] or in some cases implemented directly in hardware [2, 11] A number of investigations have been carried out for synthesis of binary logic circuits [4, 7]. Multiple Valued (MV) Logic refers to the adoption of logic systems having more than two levels [3, 9] It is generally felt that MV logic allows circuits to have increased functionality with a reduction in wiring density. In this paper we present a method for the synthesis of combinational MV ....

Iba I., Iwata M., Higuchi T: Machine Learning Approach to Gate-Level Evolvable Hardware. Proc. Of the 1 st Int. Conference on evolvable Systems: From Biology to Hardware (ICES'96), now published in Lecture Notes in Computer Science, SpringlerVerlag, Heidelberg, (1996) 118 - 135

....possibilities of designing electronic circuits using evolutionary techniques. A number of different approaches have been developed. Koza [4] showed how simple digital circuits could be evolved using Genetic Programming. This moved a step closer to actual hardware implementation when Iba et al. [3] showed how it was possible to evolve digital circuits by evolving the functionality and connectivity of interconnected AND, OR, and NOT gates for intended use on a programmable logic array device (PLA) The Swiss group at EPFL developed a cellular automaton in hardware using Xilinx 6216 FPGAs ....

Iba H., Iwata M., and Higuchi T., Machine Learning Approach to Gate-Level Evolvable Hardware, in [B], pp. 327 - 343

....algorithm for this example was surprising in several ways. Firstly, that it was possible to evolve this type of function in such a simple way, and, secondly, the way in which the actual solution deviated from the conventional design. Evolvable Hardware is a very new topic for research [4] 5][6][7] and at present is largely confined to the use of evolutionary algorithms in the synthesis of digital logic at the systems level [4] There are very few examples where researchers are actually attempting to evolve the functionality of digital circuits, and even fewer where this is being done ....

....logic at the systems level [4] There are very few examples where researchers are actually attempting to evolve the functionality of digital circuits, and even fewer where this is being done with the specific implementation platform in mind. In fact, as far as we are aware, Koza [5] and Higuchi [6] 2 head the only two other groups who have attempted to evolve actual digital circuits at gate level, and only Higuchi mentions implementation issues, and has a particular device in mind a programmable logic device or PLD. Additionally, the most complex gate level digital circuit that has been ....

H. Iba, M. Iwata and T. Higuchi, 1996, "Machine Learning Approach to Gate-Level Evolvable Hardware.", Vol. 1062 of Lecture Notes in Computer Science, Springer-Verlag, Heidelberg.

....implement a function or be merely used for routing signals. It is noteworthy that the presence of elitism significantly improves the Genetic Algorithm performance. 1. Introduction There is now a growing interest in the possibilities of designing electronic circuits using evolutionary techniques. [2, 3, 4, 5, 6, 7, 8, 10, 11, 12]. Arithmetic circuits are interesting examples to choose to use to examine the issue of evolving digital circuits [1, 9] since there are well known conventional designs with which the evolved solutions can be compared. Additionally arithmetic circuits are modular in nature so that there is ....

Iba H., Iwata M., and Higuchi T., Machine Learning Approach to Gate-Level Evolvable Hardware, in [B], pp. 327 - 343

....the greater the number of don t care inputs, the more robust (i.e. noise insensitive) the evolved hardware. Thus, we regard the number of don t care inputs as an index of MDL. The robustness of the generated hardware was achieved as a result of this improvement. The details are described in [Iba97]. 4 Discussion First of all, MDL cannot be applied to every kind of problem to be solved by GP. Representations evolved in the our experiments had the following characteristics in common. Size based Performance The more the tree grows, the better its performance (fitness) Decomposition The ....

Iba, H., Iwata,M., and Higuchi,T., A Machine Learning Approach to Gate-Level Evolvable Hardware, in International Conference on Evolutionary Systems (ICES96), Springer, 1997

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H. Iba, M. Iwata, and T. Higuchi. Machine learning approach to gate-level evolvable hardware. In T. Higuchi and M. Iwata, editors, Proceedings of the 1st International Conference on Evolvable Systems: From Biology to Hardware, volume 1259 of Lecture Notes in Computer Science, pages 327--343, Heidelberg, 1997. Springer-Verlag.

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H. Iba, M. Iwata, T. Higuchi, Machine Learning Approach to Gate-Level Evolvable Hardware, in Higuchi T. et al. (Eds.), Proceedings of The 1st Int. Conf. on Evolvable Systems: From Biology to Hardware (ICES96), Lecture Notes in Computer Science 1259: pp. 327-343, Springer-Verlag, Heidelberg, 1997.

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Iba, H., Iwata, M., Higuchi, T., "Machine Learning Approach to Gate-Level Evolvable Hardware"., Evolvable Systems: From Biology to Hardware, Lecture Notes in Computer Science 1259, pp.327-343, Springer-Verlag, 1997.

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Iba H., Iwata M., and Higuchi T. (1996) "Machine Learning Approach to Gate-Level Evolvable Hardware", in T.

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