R. E. Bryant and C.-J. H. Seger. Digital Circuit Verification using Partially-Ordered State Models. In International Symposium on Multi-Valued Logic, pages 2--7, May 1994.  Home/Search Document Details and Download
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Probabilistic Verification of Multiple-Valued Functions - Dubrova, Sack (1999) (1 citation) (Correct)
....on the problem of verification of multiple valued functions. Up to now, very little research is done in this area. Some techniques for verification of Boolean circuits, such as random simulation or symbolic simulation, can be directly applied to verification of multiple valued logic case [4] [5]. Similarly, verification procedures employing Reduced Ordered Binary Decision Diagrams (ROBDDs) 6] can adapted to Multiple valued Decision Diagrams (MDD) 7] as shown in [8] However, the MDD verification methods representing functions as single, monolithic graph might be infeasible for large ....
R. E. Bryant, C.-J. H. Seger, Digital circuit verification using partially-ordered state models, Proc. 24th Int. Symp. on Multiple-Valued Logic (1994), 2-7.
Set Manipulation with Boolean Functional Vectors - For Symbolic Reachability (2003) Self-citation (Bryant) (Correct)
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R. E. Bryant and C.-J. H. Seger. Digital Circuit Verification using Partially-Ordered State Models. In International Symposium on Multi-Valued Logic, pages 2--7, May 1994.
Set Manipulation with Boolean Functional Vectors - For Symbolic Reachability Self-citation (Bryant) (Correct)
No context found.
R. E. Bryant and C.-J. H. Seger. Digital Circuit Verification using Partially-Ordered State Models. In International Symposium on Multi-Valued Logic, pages 2--7, May 1994.
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