| J. Cong, J. Fang, and K. Khoo, "An implicit connection graph maze routing algorithm for ECO routing," in Proc. Int. Conf. Computer-Aided Design, Nov. 1999, pp. 163--167. |
....[ 16] provide a mechanism to speed up the search at the expense of suboptimal solutions. Both these techniques rely on a grid graph that restricts the search space for a router. The grid graph coincides with the grid point database. This can be expensive in terms of memory as shown by Cong et al.[17] and Hetzel [14] One approach to solve this is to ignore the grid and build the search graph on the fly[17] 18] 19] Memory is saved but time is consumed to construct the graph for every search. Hetzel[14] proposes a data structure relying on intervals for routing. He describes a fast search ....
....rely on a grid graph that restricts the search space for a router. The grid graph coincides with the grid point database. This can be expensive in terms of memory as shown by Cong et al. 17] and Hetzel [14] One approach to solve this is to ignore the grid and build the search graph on the fly[17][18] 19] Memory is saved but time is consumed to construct the graph for every search. Hetzel[14] proposes a data structure relying on intervals for routing. He describes a fast search engine that can deal with large graph sizes. Since we are seeking a balance between performance, capacity and ....
J. Cong, J. Fang, and K.-Y. Khoo, "An Implicit Connection Graph Maze Routing Algorithm for ECO Routing", Proceedings of the International Conference on ComputerAided Design, pages 163-167, 1999.
....their lengths change. Thus most properties of existing nets are preserved which is key to an effective incremental design process. Cong, Fang and Khoo presented efficient techniques for obtaining a non uniform routing grid from a given VLSI routing in order to perform incremental routing for ECO [1]. Another recent work is that of Dutt, Shanmugavel and Trimberger [4] in which an incremental rerouting algorithm was developed for fault reconfiguration in FPGAs. In their work they have used segmented FPGAs which uses i to i connection, i.e. a net is routed on only one track throughout. It ....
J.Cong, J.Fang and K.Khoo. "An Implicit Connection Graph Maze Routing Algorithm for ECO Routing".Proc. IEEE Int. Conf. Comput.- Aided Design, April 1999, pp. 12-18.
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J. Cong, J. Fang, and K. Khoo, "An implicit connection graph maze routing algorithm for ECO routing," in Proc. Int. Conf. Computer-Aided Design, Nov. 1999, pp. 163--167.
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J. Cong, J. Fang, and K.-Y. Khoo, "An implicit connection graph maze routing algorithm for ECO routing," in Proc. ACM/IEEE Int. Conf. Computer -Aided Design, Nov. 1999, pp. 163--167.
....region. For local nets, it would be the first time that they are in the routing process, so they have to be routed from sketch. An A point to point maze searching algorithm is used in the refinement process at each level. Finally, the implicit connection graph based gridless routing algorithm in [23] is applied to finalize all nets, each net routed within the corridor of the planning result. However, the MRS router has several limitations, which prohibit the multilevel routing framework from further improving the routing quality. First, the coarsening process of the MRS is too primitive. ....
....make the planning engine iterate more rounds at the coarser levels than at the finer levels to improve the quality and the run time. 1 89 16 Figure 8 The Accurate Resource Deduction 3. 4 Other Enhancements As in MRS, MARS uses the implicit connection graphbased gridless routing algorithm in [23] to finalize and evaluate the multilevel planning result. However, we made two changes to the detailed routing algorithm to better cooperate with the current multi level routing scheme. First, we added a local rip up and reroute routine to handle the failed nets. This local modification can ....
J. Cong, J. Fang, K. Khoo, "An implicit connection graph maze routing algorithm for ECO routing," Proc. International Conference on Computer Aided Design, pp. 163-167, Nov. 1999.
....In contrast, the original pins in the design are called the real pins in order to be distinguished from the pseudo pins. Dune, to support multi layer, variable width, variablespacing routing. Dune has two major components: a point to point gridless routing engine and a route plan ning engine [14, 15]. The point to point gridless routing engine is based on path searching in a non uniform grid graph stored using implcite representation. Experimental results showed that the runtime of the gridless routing engine is 2 4 times faster than that of Iroute [16, 17] a well known tile based router for ....
....engine much more closely. Experimental results show that using the route planning algorithm in our gridless detailed routing can improve the routability and also speed up the run time significantly, by a factor of 3 to 17. A detailed description of our gridless detailed router can be found in [14, 15]. 3 SUMMARY AND ONGOING WORK With a good understanding of these building blocks, we can revisit the overall flow for interconnect centric de signs, as shown in Figure 3. Our flow can be summarized as follows: In order to cope with the design complexity of giga scale integration in the nanometer ....
J. Cong, J. Fang, and K. Khoo, "An implicit connection graph maze routing algorithm for ECO routing," in Proc. A CM/IEEE International Conference on Computer Aided De- sign, pp. 163-167, Nov 1999.
....the wire length in CPPA (fi = 1 in the O(fidV ) time algorithm) In some test cases, the ones with combined cost are even faster than their via cost only counterparts. We use an internally developed multi layer gridless detailed router based on the gridless routing engine as described in [5] [7] 6] to route the above examples. This detailed router is still under refinement, it can do a net bynet routing, but can not do rip up and reroute at this point. The routing results are shown in Table III and Table IV. Please note that net counts in Tables III and IV count all the local nets ....
J. Cong, J. Fang, and K.-Y. Khoo. An implicit connection graph maze routing algorithm for ECO routing. In Proceedings of ACM/IEEE International Conference on Computer Aided Design, pages 163--167, 1999.
....algorithms successfully reduce all the noise to be smaller than 0:3 VDD . Overall, the noise control by iterative deletion algorithm is better, but the run time is also longer. We use an internally developed multi layer gridless detailed router based on the gridless routing engine presented in [4] to route the above examples. This detailed router is still under development, it can do a net by net routing, but can not do rip up and reroute. The routing results are shown in Table 2. Note that the net counts in this table are the local nets within each tile. The estimated number of vias are ....
J. Cong, J. Fang, and K.-Y. Khoo. An implicit connection graph maze routing algorithm for ECO routing. In Proceedings of ACM/IEEE International Conference on Computer Aided Design, pages 163--167, 1999.
....of the NUG graph. Our experiments show that this data structure is very efficient in memory usage while very fast in answering maze expansion related queries. The efficiency of our point to point gridless routing engine is validated when we apply it to the incremental routing problem in [74] (called the ECO problem in that paper) It was compared with the explicit uniform grid based approach and Iroute [75, 76] a well known tile based router for gridless routing, The results show that the implicit representation of the NUG graph is very efficient in memory usage, smaller than that ....
....result is shown in (d) 57 Experimental results show that using the route planning algorithm in our gridless detailed routing can improve the routability and also speed up the run time significantly, by a factor of 3 to 17. A detailed description of our gridless detailed router can be found in [73, 74]. 8 Summary and Ongoing Work In this paper, we presented our research efforts and results on developing an interconnect centric design flow. The research involves three major design phases: interconnect planning, interconnect synthesis, and interconnect layout. An efficient interconnect ....
J. Cong, J. Fang, and K. Khoo, "An implicit connection graph maze routing algorithm for ECO routing," in Proc. ACM/IEEE International Conference on Computer Aided Design, pp. 163--167, Nov 1999.
....and Iroute using seven ECO examples. 55] Their implicit approach, although very efficient in representation, is costly in computing the graph nodes. A promising approach to the single net routing problem is reported recently uses a non uniform grid graph (NUGG) with its implicit representation [5]. The graph is an orthogonal grid graph constructed based on the expansion of rectangular obstacles in the routing region according to wire via width and spacing rules. The non uniform grid graph, comparing to the one used in the uniform grid approach, is much smaller. What is more, the grid ....
....queries, a two level data structure using a first level slit tree [25, 27] plus a second level interval tree [13] is applied. The query data structure is further enhanced with a cache structure that exploits the locality of the maze expansion. The effective of this approach is validated in [5] where this graph and the auxiliary data structures is applied to the ECO problem. The paper compares the implicit graph and the query data structure with explicit uniform grid approach and Iroute, a well known tile based router for gridless routing used in the Magic layout system [1, 40] as ....
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J. Cong, J. Fang, and K.Y. Khoo. An implicit connection graph maze routing algorithm for ECO routing. In Proc. ACM/IEEE International Conference on Computer Aided Design, pages 163--167, Nov 1999.
No context found.
J. Cong, J. Fang, and K. Y. Khoo, "An implicit connection graph maze routing algorithm for ECO routing," in Proceedings of the International Conference on Computer-Aided Design, 1999, pp. 163--167.
No context found.
J.Cong, J.Fang and K.Khoo. "An Implicit Connection Graph Maze Routing Algorithm for ECO Routing".Proc. IEEE Int. Conf. Comput.- Aided Design, April 1999, pp. 12-18.
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