| Andre DeHone, Frederic Chong, Matthew Becker, Eran Egozy, Henry Minsky, Samuel Peretz, and Jr. Thomas F. Knight. Metro: A router architecture for high-performance, short-haul routing networks. In International Symposium on Computer Architecture, pages 266--277, April 1994. |
....and the channel bandwidth is 1 byte clock. Switch latency without contention is 3 cycles, wire delay between switches is 1 cycle, and a DMUX latency is 1 cycle. The DMUX also has infinite queues. A switch implementation with such parameters using full custom technology has been described in [9]. We assume that the channel data path width and the bandwidth can be increased by up to a factor of 8 without any effect on other timing parameters. 2.5 Tagged Cache and Network Interface A tagged cache is very effective for short stride prefetching. Each cache line has a flag, the prefetch bit, ....
Andre DeHone, Frederic Chong, Matthew Becker, Eran Egozy, Henry Minsky, Samuel Peretz, and Jr. Thomas F. Knight. Metro: A router architecture for high-performance, short-haul routing networks. In International Symposium on Computer Architecture, pages 266--277, April 1994.
....the virtual cut through flow control [21] Thus, if there is no contention and no previous messages in a queue, the message experiences only the minimum switch latency of 3 cycles. A message is buffered in a switch if it can not move forward. A full custom design of such a fast switch was shown in [13]. In this study, unlimited size queues are used. Other network studies have found a small difference in the performance of networks with unlimited queue size and with a reasonable queue size [6, 14] At each output port, a snapshot of all messages requesting the output port access is taken once ....
Andre DeHone, Frederic Chong, Matthew Becker, Eran Egozy, Henry Minsky, Samuel Peretz, and Jr. Thomas F. Knight. Metro: A router architecture for high-performance, short-haul routing networks. In International Symposium on Computer Architecture, pages 266--277, April 1994.
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