M. Fillo and R.B. Gillett, "Architecture and Implementation of Memory Channel 2," DEC Technical Journal, vol. 9, no. 1, July 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....translations for receive buffers. Applications are not involved in managing the TLB or maintaining translations. The U Net MM mechanism provides transparent user level DMA with arbitrary buffer spaces at the cost of added complexity in the operating system. Virtual memory mapped communication [14][39] is a user level communication mechanism that avoids the user level DMA problems by performing all communication between pairs of virtual memory pages. Instead of explicitly specifying data transfers, it forwards all modifications made to a local memory page to an associated remote page. This ....

....duration of the transfer. This pinning or locking of pages can either be done before every DMA transfer, or when the buffer is initially allocated. Existing solutions for high performance communication networks often require the application to specify the communication buffers in advance [24] 32][39]. During the buffer setup, the kernel pins the pages in physical memory, and the address mapping is made available to the I O device. In addition, the kernel can arrange the physical pages contiguously. The application is then able to initiate DMA transfers using this prearranged buffer without ....

M. Fillo and R.B. Gillett, "Architecture and Implementation of Memory Channel 2," DEC Technical Journal, vol. 9, no. 1, July 1997.

....use for our parallel applications is an AlphaServer system. Each node is an AlphaServer 4100 5 600, with four 600 MHz 21164A processors, an 8 MB direct mapped board level cache with a 64 byte linesize, and 2 GBytes of memory, running Tru64 Unix 4.0F. The nodes are connected by a Memory Channel 2 [13] system area network, which is used for tightly coupled sharing. Connection to the local area network is via TCP IP over Fast Ethernet. We also use Sun Ultra 5 workstations with 400 MHz Sparc v9 processors with 128 MB of memory,running SunOS 5.7, and 333 MHz Celeron PCs with 256 MB of memory, ....

M. Fillo and R. B. Gillett. Architecture and Implementation of Memory Channel 2. Digital Technical Journal,9(1):27--41, 1997.

....Barnes Hut simulation. The simulation runs on a 4 node, 16 processor Cashmere system. Each node is an AlphaServer 4100 5 600, with four 600 MHz 21164A processors, an 8 MB directmapped board level cache with a 64 byte line size, and 2 GBytes of memory. The nodes are connected by a Memory Channel 2 [13] system area network. The simulation repeatedly computes new positions for 16,000 bodies. These positions may be shared with a remote visualization satellite via an InterWeave segment. The simulator uses a write lock to update the shared segment, while the satellite uses a relaxed read lock with ....

M. Fillo and R. B. Gillett. Architecture and Implementation of Memory Channel 2. Digital Technical Journal, 9(1):27--41, 1997.

....Barnes Hut simulation. The simulation runs on a 4 node, 16 processor Cashmere system. Each node is an AlphaServer 4100 5 600, with four 600 MHz 21164A processors, an 8 MB direct mapped board level cache with a 64 byte line size, and 2 GBytes of memory. The nodes are connected by a Memory Channel 2 [13] system area network. The simulation repeatedly computes new positions for 16,000 bodies. These positions may be shared with a remote visualization satellite via an InterWeave segment. The simulator uses a writer lock to update the shared segment, while the satellite uses a relaxed reader lock ....

M. Fillo and R. B. Gillett. Architecture and Implementation of Memory Channel 2. Digital Technical Journal, 9(1):27--41, 1997.

.... csm protocol Protocol csm synch Synchronization csm message Messaging csm misc Miscellaneous csm services Services Figure 1: Cashmere organization. The Cashmere prototype has been implemented on a cluster of Compaq AlphaServer SMPs connected by a Compaq Memory Channel network [3, 4]. The prototype is designed to leverage the hardware coherence available within SMPs and also the special network features that may lower communication overhead. In this paper, we will discuss the implementation of two Cashmere versions that are designed to isolate the impact of the special ....

....the details of this paper, the reader is strongly encouraged to read two earlier Cashmere papers [8, 7] These papers provide good overviews of the Cashmere protocol and provide details of its implementation. A good understanding of the Cashmere protocol and also of the Memory Channel network [3, 4] are essential in understanding the implementation details. In the rest of this Section, we will briefly introduce terms and concepts that the reader must understand before proceeding. Memory Channel Cashmere attempts to leverage the special network features of the Memory Channel network. The ....

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M. Fillo and R. B. Gillett. Architecture and Implementation of Memory Channel 2. Digital Technical Journal, 9(1):27--41, 1997.

....and pricable cluster nodes are already available due to today s Intel P6based PCs and Alpha based workstations, SAN technology is still evolving and relatively expensive. In the last years, several SANs have pushed PC based Cluster Computing ahead, namely ServerNet, Myrinet, SCI, Memory Channel [1], and Synfinity [2] A closer look at various performance measurements shows that several SAN implementations need a relatively large message size to deliver an appropriate bandwidth. The typical bandwidth curves start with moderate values and begin to rise at message sizes of 4 8 Kbyte. But a ....

M. Fillo and R. B. Gillett. Architecture and implementation of MEMORY CHANNEL 2. Digital Technical Journal of Digital Equipment Corporation, 9(1):27--41, August 1997.

....Projects such as GAMMA from the University of Genoa [8] have shown that by reducing the operating system overhead, the latency associated with communications can be significantly reduced, even on commodity hardware. Other projects, such as Myricom s Myrinet [6] and DEC Compaq s Memory Channel [14], show that a different network interface architecture can also yield significant performance gains. By taking advantage of modern, high performance, highly integrated microcontrollers, future network card designs could realize even higher performance through lower operating system overhead and ....

....are to be eliminated, however, functions that they provide must somehow be transferred elsewhere in the system. Recognition of this fact has lead to many different user level network interfaces, such as Myricom s Myrinet [6] Princeton s SHRIMP [5] MIT s Star T X [16] DEC Compaq s Memory Channel [14], and others. What these systems attempt to do is to allow individual processes to have direct contact with the network interface, thereby eliminating expensive operating system calls. However, reducing latency is not the only important characteristic. In systems such as Memory Channel, data is ....

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M. Fillo and R. B. Gillett. Architecture and implementation of MEMORY CHANNEL 2. Digital Technical Journal, 9(1), 1997.

....A. Hopper y Olivetti and Oracle Research Laboratory y Cambridge University Engineering Department Trumpington Street, Cambridge, England. fsjhodges, spope, droberts, gmapp, ahopperg orl.co. uk Abstract Memory mapped networks such as Scalable Coherent Interconnect (SCI) 5] and Memory Channel [4] offer a new method for constructing network peripherals by remoting a host s IO bus. This paper details our experiences from building such an endpoint, and examines how greater support may be provided. 1 Introduction At ORL we have experimented with an exploded workstation configuration, where ....

M. Fillo and R. Gillett. Architecture and Implementation of Memory Channel 2. Digital Technical Journal, 9(1), 1997.

....widely accepted as beneficial while fine grain mechanisms remain controversial. Since efficient bulk transfer requires DMA, it has been natural to make the network interface design memory centric with support for small messages a secondary consideration. Memory based interfaces in multicomputers [6, 9, 66, 69, 72, 24] and workstations [17, 19, 76, 77] limit the performance of the interface to the speed of memory, but provide easy protection for multiprogramming if the network interface also demultiplexes messages into per process buffers. Automatic hardware buffering also deals well with sinking bursts of ....

....of a performance requirement since hardware handles the common cases. Sender based message systems use network interfaces in memory but allow the sending processor to participate in managing the receiving processor s memory. Remote memory communication as in SHRIMP [6] and the DEC memory channel [24] give a sending process the means to directly write memory in another process on another processor. More elaborate sender based models as in Hamlyn [81, 9] and Hybrid Deposit [59] support more communication options, e.g. the ability to insert into a remote queue, but retain the idea that the ....

Marco Fillo and Richard B. Gillett. Architecture and Implementation of Memory Channel 2. Digital Technical Journal, 9(1):27--41, 1997.

....Research Program (C.R. E901010001) Supported in part by the European Commission, the TMR Program. Also associated with University of Copenhagen (Denmark) 2 Povl T. Koch, Xavier Rousset de Pina latencies of a few microseconds, and hardware based reliable delivery and congestion control [1, 7, 10, 20, 24]. After the setup of remote memory mappings, all communication is handled through the processor s normal load and store instructions or system managed DMA with very little overhead on the sending and receiving processors. These types of interfaces have been shown to be well suited for ....

....store capabilities on the TurboChannel I O bus. They explicitly support shared memory implementation by providing multicasting for directories and update based memory protocols and page access counters that can trigger alarms when a specified threshold is exceeded. Digital s Memory Channel [10] provides a mainly remote write interface. In the second generation implementation of Memory Channel, remote reads can be performed using special mappings: a write to remote location can trigger the write of that value to a local location. Princeton s SHRIMP [1] is based on the principle that ....

Marco Fillo and Richard B. Gillett. Architecture and implementation of MEMORY CHANNEL. Digital Technical Journal, 9(1):27--41, 1997.

....E mail: scios inrialpes.fr. P. Koch is also associated with the University of Copenhagen (Denmark) a parallel architecture because only problems with coarsergrained parallelism can be solved efficiently. With the advent of I O based SCI, e.g. Dolphin s PCISCI adapter [6] and similar interfaces [8], 18] with very low latencies, it is now possible to solve much finer grained problems using a shared memory abstraction. With the appropriate techniques, we believe that a NOW with an I O based SCI interface, an SCI cluster, can perform almost as well as an SMP or CC NUMA for a wide range of ....

Marco Fillo and Richard B. Gillett. Architecture and implementation of MEMORY CHANNEL. Digital Technical Journal, 9(1):27--41, 1997.

....Engineering Department Trumpington Street, Cambridge, England. spope, sjhodges, gmapp, droberts, ahopper orl.co. uk May 27, 1998 Abstract Recently several network technologies which support user level communication between processes using a shared memory interface have become available [4, 7]. These technologies o#er very low latency, high bandwidth communication by eliminating the need for software protocol stacks. Whilst there has been much research on the use of such networks in the context of parallel computing [5, 6, 13] relatively little work has been done on their suitability ....

M. Fillo and R. Gillett. Architecture and Implementation of Memory Channel 2. Digital Technical Journal, 9(1), 1997.

....delivering 50 to 80 of bus bandwidth. Measurements with a Pamette PCI device [20] show that Digital s CIA bridge can burst consecutive PIO writes issued by the 21164 Alpha CPU on the PCI bus, for a bandwidth of 96 MB s. In fact, Digital uses PIO exclusively for writing data to the MemoryChannel [15] network. To burst PIO on the receiving side, the processor must aggregate loads and present larger requests to the bridge. The 21164 CPU and CIA bridge can issue PIO reads in 32 byte bursts to deliver bandwidths of 47 MB s 2 Alcor Miata, 8320 byte MTU, 1M netperf transfers, socket buffers at ....

Marco Fillo and Richard B. Gillett. Architecture and implementation of MEMORY CHANNEL2. Digital Technical Journal, 9(1), 1997.

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